Searched refs:regUVD_VCPU_CACHE_SIZE0 (Results 1 – 5 of 5) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vcn_v4_0_3.c | 361 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); in vcn_v4_0_3_mc_resume()
450 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
453 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
925 regUVD_VCPU_CACHE_SIZE0), in vcn_v4_0_3_start_sriov()
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| H A D | vcn_v4_0.c | 399 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); in vcn_v4_0_mc_resume()
478 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
481 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1295 regUVD_VCPU_CACHE_SIZE0), in vcn_v4_0_start_sriov()
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_2_6_0_offset.h | 32 #define regUVD_VCPU_CACHE_SIZE0 … macro
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| H A D | vcn_4_0_0_offset.h | 380 #define regUVD_VCPU_CACHE_SIZE0 … macro
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| H A D | vcn_4_0_3_offset.h | 382 #define regUVD_VCPU_CACHE_SIZE0 … macro
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