Searched refs:regUVD_VCPU_CACHE_OFFSET1 (Results 1 – 5 of 5) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vcn_v4_0_3.c | 382 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v4_0_3_mc_resume()
478 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
485 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
950 regUVD_VCPU_CACHE_OFFSET1), 0); in vcn_v4_0_3_start_sriov()
|
| H A D | vcn_v4_0.c | 406 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v4_0_mc_resume()
492 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
499 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1306 regUVD_VCPU_CACHE_OFFSET1), in vcn_v4_0_start_sriov()
|
| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_2_6_0_offset.h | 34 #define regUVD_VCPU_CACHE_OFFSET1 … macro
|
| H A D | vcn_4_0_0_offset.h | 382 #define regUVD_VCPU_CACHE_OFFSET1 … macro
|
| H A D | vcn_4_0_3_offset.h | 384 #define regUVD_VCPU_CACHE_OFFSET1 … macro
|