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Searched refs:regUVD_SUVD_CGC_CTRL (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c605 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); in vcn_v4_0_3_disable_clock_gating()
614 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); in vcn_v4_0_3_disable_clock_gating()
665 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
707 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); in vcn_v4_0_3_enable_clock_gating()
716 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); in vcn_v4_0_3_enable_clock_gating()
H A Dvcn_v4_0.c751 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); in vcn_v4_0_disable_clock_gating()
762 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); in vcn_v4_0_disable_clock_gating()
819 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
867 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); in vcn_v4_0_enable_clock_gating()
878 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); in vcn_v4_0_enable_clock_gating()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1256 #define regUVD_SUVD_CGC_CTRL … macro
H A Dvcn_4_0_0_offset.h150 #define regUVD_SUVD_CGC_CTRL … macro
H A Dvcn_4_0_3_offset.h150 #define regUVD_SUVD_CGC_CTRL … macro