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Searched refs:regUVD_STATUS (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c910 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS), in vcn_v4_0_3_start_sriov()
1076 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | in vcn_v4_0_3_start()
1078 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); in vcn_v4_0_3_start()
1156 regUVD_STATUS); in vcn_v4_0_3_start()
1191 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, in vcn_v4_0_3_start()
1284 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, in vcn_v4_0_3_stop()
1333 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); in vcn_v4_0_3_stop()
1485 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == in vcn_v4_0_3_is_idle()
1505 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, in vcn_v4_0_3_wait_for_idle()
1531 regUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v4_0_3_set_clockgating_state()
H A Dvcn_v4_0.c314 RREG32_SOC15(VCN, i, regUVD_STATUS))) { in vcn_v4_0_hw_fini()
1063 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v4_0_start()
1064 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); in vcn_v4_0_start()
1138 status = RREG32_SOC15(VCN, i, regUVD_STATUS); in vcn_v4_0_start()
1181 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, in vcn_v4_0_start()
1265 regUVD_STATUS), in vcn_v4_0_start_sriov()
1474 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v4_0_stop()
1519 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); in vcn_v4_0_stop()
1879 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v4_0_is_idle()
1901 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, in vcn_v4_0_wait_for_idle()
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1228 #define regUVD_STATUS … macro
H A Dvcn_4_0_0_offset.h350 #define regUVD_STATUS … macro
H A Dvcn_4_0_3_offset.h352 #define regUVD_STATUS … macro