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Searched refs:regUVD_RB_WPTR (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0.c1015 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); in vcn_v4_0_start_dpg_mode()
1018 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); in vcn_v4_0_start_dpg_mode()
1019 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); in vcn_v4_0_start_dpg_mode()
1198 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); in vcn_v4_0_start()
1201 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); in vcn_v4_0_start()
1202 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); in vcn_v4_0_start()
1440 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); in vcn_v4_0_stop_dpg_mode()
1618 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); in vcn_v4_0_unified_ring_get_wptr()
1639 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v4_0_unified_ring_set_wptr()
H A Dvcn_v4_0_3.c834 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); in vcn_v4_0_3_start_dpg_mode()
835 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); in vcn_v4_0_3_start_dpg_mode()
1197 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); in vcn_v4_0_3_start()
1203 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); in vcn_v4_0_3_start()
1231 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); in vcn_v4_0_3_stop_dpg_mode()
1380 regUVD_RB_WPTR); in vcn_v4_0_3_unified_ring_get_wptr()
1401 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, in vcn_v4_0_3_unified_ring_set_wptr()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1320 #define regUVD_RB_WPTR … macro
H A Dvcn_4_0_0_offset.h1314 #define regUVD_RB_WPTR … macro
H A Dvcn_4_0_3_offset.h1242 #define regUVD_RB_WPTR … macro