Home
last modified time | relevance | path

Searched refs:regUVD_MPC_SET_MUXB0 (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1046 #define regUVD_MPC_SET_MUXB0 … macro
H A Dvcn_4_0_0_offset.h462 #define regUVD_MPC_SET_MUXB0 … macro
H A Dvcn_4_0_3_offset.h464 #define regUVD_MPC_SET_MUXB0 … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c781 VCN, 0, regUVD_MPC_SET_MUXB0), in vcn_v4_0_3_start_dpg_mode()
1107 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0, in vcn_v4_0_3_start()
H A Dvcn_v4_0.c969 VCN, inst_idx, regUVD_MPC_SET_MUXB0), in vcn_v4_0_start_dpg_mode()
1108 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, in vcn_v4_0_start()