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Searched refs:regUVD_MPC_SET_MUXA0 (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1042 #define regUVD_MPC_SET_MUXA0 … macro
H A Dvcn_4_0_0_offset.h458 #define regUVD_MPC_SET_MUXA0 … macro
H A Dvcn_4_0_3_offset.h460 #define regUVD_MPC_SET_MUXA0 … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c774 VCN, 0, regUVD_MPC_SET_MUXA0), in vcn_v4_0_3_start_dpg_mode()
1100 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0, in vcn_v4_0_3_start()
H A Dvcn_v4_0.c962 VCN, inst_idx, regUVD_MPC_SET_MUXA0), in vcn_v4_0_start_dpg_mode()
1101 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, in vcn_v4_0_start()