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Searched refs:regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c373 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v4_0_3_mc_resume()
478 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v4_0_3_mc_resume_dpg_mode()
942 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr)); in vcn_v4_0_3_start_sriov()
H A Dvcn_v4_0.c410 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v4_0_mc_resume()
506 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v4_0_mc_resume_dpg_mode()
1315 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v4_0_start_sriov()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h310 #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW macro
H A Dvcn_4_0_0_offset.h676 #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW macro
H A Dvcn_4_0_3_offset.h678 #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW macro