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Searched refs:regUVD_CGC_GATE (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c549 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE); in vcn_v4_0_3_disable_clock_gating()
563 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE, data); in vcn_v4_0_3_disable_clock_gating()
564 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v4_0_3_disable_clock_gating()
657 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
H A Dvcn_v4_0.c676 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); in vcn_v4_0_disable_clock_gating()
698 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); in vcn_v4_0_disable_clock_gating()
699 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v4_0_disable_clock_gating()
811 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1244 #define regUVD_CGC_GATE … macro
H A Dvcn_4_0_0_offset.h32 #define regUVD_CGC_GATE … macro
H A Dvcn_4_0_3_offset.h32 #define regUVD_CGC_GATE … macro