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Searched refs:regUVD_CGC_CTRL (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c529 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_disable_clock_gating()
533 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_disable_clock_gating()
552 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_disable_clock_gating()
565 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_disable_clock_gating()
639 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
673 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_enable_clock_gating()
677 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_enable_clock_gating()
679 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); in vcn_v4_0_3_enable_clock_gating()
691 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); in vcn_v4_0_3_enable_clock_gating()
H A Dvcn_v4_0.c670 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_disable_clock_gating()
674 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_disable_clock_gating()
701 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_disable_clock_gating()
722 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_disable_clock_gating()
807 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
838 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_enable_clock_gating()
842 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_enable_clock_gating()
844 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_enable_clock_gating()
865 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); in vcn_v4_0_enable_clock_gating()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1248 #define regUVD_CGC_CTRL … macro
H A Dvcn_4_0_0_offset.h34 #define regUVD_CGC_CTRL … macro
H A Dvcn_4_0_3_offset.h34 #define regUVD_CGC_CTRL … macro