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Searched refs:regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v6_0.c482 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); in sdma_v6_0_gfx_resume()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_offset.h51 #define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_3_offset.h52 #define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL … macro
H A Dgc_11_0_0_offset.h52 #define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL … macro