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Searched refs:regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h349 #define regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX … macro
H A Dgc_11_0_3_offset.h355 #define regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX … macro