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Searched refs:regRLC_SPARE_INT_0 (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h10590 #define regRLC_SPARE_INT_0 … macro
H A Dgc_11_0_3_offset.h11220 #define regRLC_SPARE_INT_0 … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c685 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v11_0_init_rlcg_reg_access_ctrl()