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Searched refs:regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h7210 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 … macro
H A Ddpcs_4_2_0_offset.h128 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 … macro
H A Ddpcs_4_2_2_offset.h115 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 … macro
H A Ddpcs_4_2_3_offset.h132 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h12463 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 … macro
H A Ddcn_3_1_5_offset.h12328 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 … macro
H A Ddcn_3_1_4_offset.h11576 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 … macro
H A Ddcn_3_1_6_offset.h13059 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 … macro