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Searched refs:regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h7207 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX … macro
H A Ddpcs_4_2_0_offset.h125 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX … macro
H A Ddpcs_4_2_2_offset.h112 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX … macro
H A Ddpcs_4_2_3_offset.h129 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h12460 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12325 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h11573 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13056 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX … macro