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Searched refs:regPWRSEQ0_BL_PWM_PERIOD_CNTL (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h7172 #define regPWRSEQ0_BL_PWM_PERIOD_CNTL … macro
H A Ddpcs_4_2_0_offset.h90 #define regPWRSEQ0_BL_PWM_PERIOD_CNTL … macro
H A Ddpcs_4_2_2_offset.h77 #define regPWRSEQ0_BL_PWM_PERIOD_CNTL … macro
H A Ddpcs_4_2_3_offset.h94 #define regPWRSEQ0_BL_PWM_PERIOD_CNTL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h12425 #define regPWRSEQ0_BL_PWM_PERIOD_CNTL … macro
H A Ddcn_3_1_5_offset.h12290 #define regPWRSEQ0_BL_PWM_PERIOD_CNTL … macro
H A Ddcn_3_1_4_offset.h11538 #define regPWRSEQ0_BL_PWM_PERIOD_CNTL … macro
H A Ddcn_3_1_6_offset.h13021 #define regPWRSEQ0_BL_PWM_PERIOD_CNTL … macro