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Searched refs:regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h6261 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX … macro
H A Ddpcs_4_2_0_offset.h591 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX … macro
H A Ddpcs_4_2_2_offset.h598 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX … macro
H A Ddpcs_4_2_3_offset.h634 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h11806 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h11551 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h10919 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h10949 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h10940 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h12042 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX … macro