Home
last modified time | relevance | path

Searched refs:regCP_MQD_BASE_ADDR (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v11.c195 hqd_base = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR); in hqd_load_v11()
332 for (reg = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR); in hqd_dump_v11()
H A Damdgpu_amdkfd_gc_9_4_3.c299 hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR); in kgd_gfx_v9_4_3_hqd_load()
H A Dmes_v11_0.c834 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); in mes_v11_0_queue_init_register()
H A Dgfx_v9_4_3.c1640 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, in gfx_v9_4_3_xcc_kiq_init_register()
H A Dgfx_v11_0.c3914 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, in gfx_v11_0_kiq_init_register()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h693 #define regCP_MQD_BASE_ADDR … macro
H A Dgc_9_4_3_offset.h3282 #define regCP_MQD_BASE_ADDR … macro
H A Dgc_11_0_0_offset.h4600 #define regCP_MQD_BASE_ADDR … macro
H A Dgc_11_0_3_offset.h4824 #define regCP_MQD_BASE_ADDR … macro