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Searched refs:regCP_ME_IC_OP_CNTL (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2025 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2027 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache()
2031 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2299 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2312 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2314 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2318 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
3000 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3013 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3015 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h9724 #define regCP_ME_IC_OP_CNTL … macro
H A Dgc_11_0_3_offset.h10284 #define regCP_ME_IC_OP_CNTL … macro