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Searched refs:regCP_ME_CNTL (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2220 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2227 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2236 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2343 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_me_cache_rs64()
2350 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2359 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2504 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
2507 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2512 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2526 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h196 #define regCP_ME_CNTL … macro
H A Dgc_9_4_2_offset.h239 #define regCP_ME_CNTL … macro
H A Dgc_11_0_3_offset.h6478 #define regCP_ME_CNTL … macro
H A Dgc_11_0_0_offset.h6198 #define regCP_ME_CNTL … macro