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Searched refs:regCP_HQD_PQ_WPTR_POLL_ADDR_HI (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gc_9_4_3.c346 regCP_HQD_PQ_WPTR_POLL_ADDR_HI), in kgd_gfx_v9_4_3_hqd_load()
H A Damdgpu_amdkfd_gfx_v11.c240 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), in hqd_load_v11()
H A Dmes_v11_0.c858 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, in mes_v11_0_queue_init_register()
H A Dgfx_v9_4_3.c1668 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v9_4_3_xcc_kiq_init_register()
H A Dgfx_v11_0.c3942 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v11_0_kiq_init_register()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h721 #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI macro
H A Dgc_9_4_3_offset.h3310 #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI macro
H A Dgc_11_0_0_offset.h4628 #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI macro
H A Dgc_11_0_3_offset.h4852 #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI macro