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Searched refs:regCPC_INT_STATUS (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h573 #define regCPC_INT_STATUS … macro
H A Dgc_9_4_3_offset.h3034 #define regCPC_INT_STATUS … macro
H A Dgc_11_0_0_offset.h4320 #define regCPC_INT_STATUS … macro
H A Dgc_11_0_3_offset.h4544 #define regCPC_INT_STATUS … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c2644 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); in gfx_v9_4_3_ring_emit_fence_kiq()
H A Dgfx_v11_0.c5455 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); in gfx_v11_0_ring_emit_fence_kiq()