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Searched refs:reg (Results 1 – 25 of 2224) sorted by relevance

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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c70 u32 reg; in wait_refresh_op_complete() local
74 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in wait_refresh_op_complete()
76 } while (reg); /* Wait for '0' */ in wait_refresh_op_complete()
116 u32 reg, freq_par, tmp; in ddr3_dfs_high_2_low() local
132 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
134 reg |= (1 << REG_DFS_DLLNEXTSTATE_OFFS); in ddr3_dfs_high_2_low()
135 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
141 reg = reg_read(REG_METAL_MASK_ADDR); in ddr3_dfs_high_2_low()
143 reg &= ~(1 << REG_METAL_MASK_RETRY_OFFS); in ddr3_dfs_high_2_low()
145 dfs_reg_write(REG_METAL_MASK_ADDR, reg); in ddr3_dfs_high_2_low()
[all …]
H A Dddr3_write_leveling.c66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
75 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_write_leveling_hw()
76 if (reg & (1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)) { in ddr3_write_leveling_hw()
79 reg & ~(1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)); in ddr3_write_leveling_hw()
83 reg = 1 << REG_DRAM_TRAINING_WL_OFFS; in ddr3_write_leveling_hw()
85 reg |= (COUNT_HW_WL << REG_DRAM_TRAINING_RETEST_OFFS); in ddr3_write_leveling_hw()
86 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
87 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
89 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) | in ddr3_write_leveling_hw()
91 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg); in ddr3_write_leveling_hw()
[all …]
H A Dddr3_hw_training.c83 u32 freq, reg; in ddr3_hw_training() local
105 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
106 if (reg & (1 << REG_SDRAM_CONFIG_ECC_OFFS)) { in ddr3_hw_training()
108 reg |= (1 << REG_SDRAM_CONFIG_IERR_OFFS); in ddr3_hw_training()
109 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_hw_training()
114 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
115 if (reg & (1 << REG_SDRAM_CONFIG_REGDIMM_OFFS)) in ddr3_hw_training()
123 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_hw_training()
124 dram_info.mode_2t = (reg >> REG_DUNIT_CTRL_LOW_2T_OFFS) & in ddr3_hw_training()
129 reg = reg_read(REG_DDR3_MR0_ADDR) >> 2; in ddr3_hw_training()
[all …]
H A Dddr3_spd.c576 u32 reg, tmp, cwl; local
697 reg = (reg_read(REG_DDR3_MR0_ADDR) >> 2);
698 reg = ((((reg >> 1) & 0xE)) | (reg & 0x1)) & 0xF;
702 dimm_num, ddr3_valid_cl_to_cl(reg));
712 reg = 0x73004000;
717 reg |= (1 << REG_SDRAM_CONFIG_ECC_OFFS);
718 reg |= (1 << REG_SDRAM_CONFIG_IERR_OFFS);
729 reg |= (1 << REG_SDRAM_CONFIG_REGDIMM_OFFS);
741 reg |= (1 << REG_SDRAM_CONFIG_WIDTH_OFFS);
752 reg |= (1 << REG_SDRAM_CONFIG_WIDTH_OFFS);
[all …]
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_dp_lowlevel.c22 unsigned int reg; in exynos_dp_enable_video_input() local
24 reg = readl(&dp_regs->video_ctl1); in exynos_dp_enable_video_input()
25 reg &= ~VIDEO_EN_MASK; in exynos_dp_enable_video_input()
29 reg |= VIDEO_EN_MASK; in exynos_dp_enable_video_input()
31 writel(reg, &dp_regs->video_ctl1); in exynos_dp_enable_video_input()
39 unsigned int reg; in exynos_dp_enable_video_bist() local
41 reg = readl(&dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
42 reg &= ~VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
46 reg |= VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
48 writel(reg, &dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
[all …]
H A Dexynos_mipi_dsi_lowlevel.c20 unsigned int reg; in exynos_mipi_dsi_func_reset() local
25 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
27 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_func_reset()
29 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
34 unsigned int reg = 0; in exynos_mipi_dsi_sw_reset() local
39 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
41 reg |= DSIM_SWRST; in exynos_mipi_dsi_sw_reset()
42 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_sw_reset()
44 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
51 unsigned int reg = readl(&mipi_dsim->intsrc); in exynos_mipi_dsi_sw_release() local
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-38x-controlcenterdc.dts59 reg = <0x00000000 0x10000000>; /* 256 MB */
81 reg = <0x21>;
88 reg = <0x22>;
94 reg = <0x23>;
100 reg = <0x24>;
106 reg = <0x25>;
112 reg = <0x26>;
123 reg = <0x29>;
130 reg = <0x2d>;
132 reg = <0>;
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dwarmboot_avp.c34 u32 reg; in wb_start() local
42 : "=r"(reg) /* output */ in wb_start()
46 if (reg != NV_WB_RUN_ADDRESS) in wb_start()
55 reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]); in wb_start()
56 reg |= SWR_CSITE_RST; in wb_start()
57 writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]); in wb_start()
68 reg = PWRGATE_TOGGLE_PARTID_CPU | PWRGATE_TOGGLE_START; in wb_start()
69 writel(reg, &pmc->pmc_pwrgate_toggle); in wb_start()
75 reg = readl(&pmc->pmc_remove_clamping); in wb_start()
76 reg |= CPU_CLMP; in wb_start()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dfsl_lsch2_serdes.c150 u32 cfg_tmp, reg = 0; in setup_serdes_volt() local
180 reg = in_be32(&serdes1_base->lane[i].gcr0); in setup_serdes_volt()
181 reg &= 0xFF9FFFFF; in setup_serdes_volt()
182 out_be32(&serdes1_base->lane[i].gcr0, reg); in setup_serdes_volt()
190 reg = in_be32(&serdes2_base->lane[i].gcr0); in setup_serdes_volt()
191 reg &= 0xFF9FFFFF; in setup_serdes_volt()
192 out_be32(&serdes2_base->lane[i].gcr0, reg); in setup_serdes_volt()
200 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
201 reg &= 0xFFFFFFBF; in setup_serdes_volt()
202 reg |= 0x10000000; in setup_serdes_volt()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c29 u32 reg; in enable_ocotp_clk() local
31 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
33 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK; in enable_ocotp_clk()
35 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK; in enable_ocotp_clk()
36 __raw_writel(reg, &imx_ccm->CCGR2); in enable_ocotp_clk()
83 u32 reg; in enable_usboh3_clk() local
85 reg = __raw_readl(&imx_ccm->CCGR6); in enable_usboh3_clk()
87 reg |= MXC_CCM_CCGR6_USBOH3_MASK; in enable_usboh3_clk()
89 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK); in enable_usboh3_clk()
90 __raw_writel(reg, &imx_ccm->CCGR6); in enable_usboh3_clk()
[all …]
/openbmc/qemu/include/hw/
H A Dregisterfields.h21 #define REG32(reg, addr) \ argument
22 enum { A_ ## reg = (addr) }; \
23 enum { R_ ## reg = (addr) / 4 };
25 #define REG8(reg, addr) \ argument
26 enum { A_ ## reg = (addr) }; \
27 enum { R_ ## reg = (addr) };
29 #define REG16(reg, addr) \ argument
30 enum { A_ ## reg = (addr) }; \
31 enum { R_ ## reg = (addr) / 2 };
33 #define REG64(reg, addr) \ argument
[all …]
/openbmc/u-boot/drivers/watchdog/
H A Dorion_wdt.c25 void __iomem *reg; member
47 writel(priv->timeout, priv->reg + priv->wdt_counter_offset); in orion_wdt_reset()
55 u32 reg; in orion_wdt_start() local
60 reg = readl(priv->reg + TIMER_CTRL); in orion_wdt_start()
61 reg |= WDT_AXP_FIXED_ENABLE_BIT; in orion_wdt_start()
62 writel(reg, priv->reg + TIMER_CTRL); in orion_wdt_start()
65 writel(priv->timeout, priv->reg + priv->wdt_counter_offset); in orion_wdt_start()
68 reg = readl(priv->reg + TIMER_A370_STATUS); in orion_wdt_start()
69 reg &= ~WDT_A370_EXPIRED; in orion_wdt_start()
70 writel(reg, priv->reg + TIMER_A370_STATUS); in orion_wdt_start()
[all …]
/openbmc/u-boot/board/micronas/vct/
H A Dtop.c13 u32 reg; member
28 TOP_PINMUX_t reg; in top_read_pin() local
35 reg.reg = 0xdeadbeef; in top_read_pin()
38 reg.reg = reg_read(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE)); in top_read_pin()
41 reg.reg = reg_read(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE)); in top_read_pin()
44 reg.reg = reg_read(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE)); in top_read_pin()
47 reg.reg = reg_read(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE)); in top_read_pin()
56 reg.reg = reg_read(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS + in top_read_pin()
60 reg.reg = reg_read(TOP_BASE + (pin * 4)); in top_read_pin()
64 return reg; in top_read_pin()
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-quark/
H A Dmsg_port.h44 void msg_port_setup(int op, int port, int reg);
54 u32 msg_port_read(u8 port, u32 reg);
63 void msg_port_write(u8 port, u32 reg, u32 value);
73 u32 msg_port_alt_read(u8 port, u32 reg);
82 void msg_port_alt_write(u8 port, u32 reg, u32 value);
92 u32 msg_port_io_read(u8 port, u32 reg);
101 void msg_port_io_write(u8 port, u32 reg, u32 value);
108 #define msg_port_generic_clrsetbits(type, port, reg, clr, set) \ argument
109 msg_port_##type##_write(port, reg, \
110 (msg_port_##type##_read(port, reg) \
[all …]
/openbmc/u-boot/board/freescale/common/
H A Dpfuze.c54 unsigned int reg; in pfuze_common_init() local
65 pmic_reg_read(p, PFUZE100_DEVICEID, &reg); in pfuze_common_init()
66 printf("PMIC: PFUZE100 ID=0x%02x\n", reg); in pfuze_common_init()
69 pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg); in pfuze_common_init()
70 reg &= ~SW1x_STBY_MASK; in pfuze_common_init()
71 reg |= SW1x_0_975V; in pfuze_common_init()
72 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); in pfuze_common_init()
75 pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg); in pfuze_common_init()
76 reg &= ~SW1xCONF_DVSSPEED_MASK; in pfuze_common_init()
77 reg |= SW1xCONF_DVSSPEED_4US; in pfuze_common_init()
[all …]
/openbmc/u-boot/drivers/pci/
H A Dpci-aardvark.c121 #define PCIE_CONF_REG(reg) ((reg) & 0xffc) argument
150 static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg) in advk_writel() argument
152 writel(val, pcie->base + reg); in advk_writel()
155 static inline uint advk_readl(struct pcie_advk *pcie, uint reg) in advk_readl() argument
157 return readl(pcie->base + reg); in advk_readl()
224 uint reg; in pcie_advk_check_pio_status() local
228 reg = advk_readl(pcie, PIO_STAT); in pcie_advk_check_pio_status()
229 status = (reg & PIO_COMPLETION_STATUS_MASK) >> in pcie_advk_check_pio_status()
234 if (reg & PIO_ERR_STATUS) { in pcie_advk_check_pio_status()
273 if (reg & PIO_NON_POSTED_REQ) in pcie_advk_check_pio_status()
[all …]
/openbmc/u-boot/drivers/spi/
H A Dcadence_qspi_apb.c189 unsigned int reg; in cadence_qspi_apb_controller_enable() local
190 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
191 reg |= CQSPI_REG_CONFIG_ENABLE; in cadence_qspi_apb_controller_enable()
192 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
197 unsigned int reg; in cadence_qspi_apb_controller_disable() local
198 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
199 reg &= ~CQSPI_REG_CONFIG_ENABLE; in cadence_qspi_apb_controller_disable()
200 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
233 unsigned int reg; in cadence_qspi_apb_readdata_capture() local
236 reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE); in cadence_qspi_apb_readdata_capture()
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_gen5.c320 u32 reg, clock; in cm_get_main_vco_clk_hz() local
323 reg = readl(&clock_manager_base->main_pll.vco); in cm_get_main_vco_clk_hz()
325 clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> in cm_get_main_vco_clk_hz()
327 clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >> in cm_get_main_vco_clk_hz()
335 u32 reg, clock = 0; in cm_get_per_vco_clk_hz() local
338 reg = readl(&clock_manager_base->per_pll.vco); in cm_get_per_vco_clk_hz()
339 reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >> in cm_get_per_vco_clk_hz()
341 if (reg == CLKMGR_VCO_SSRC_EOSC1) in cm_get_per_vco_clk_hz()
343 else if (reg == CLKMGR_VCO_SSRC_EOSC2) in cm_get_per_vco_clk_hz()
345 else if (reg == CLKMGR_VCO_SSRC_F2S) in cm_get_per_vco_clk_hz()
[all …]
/openbmc/u-boot/drivers/video/
H A Dipu_disp.c183 u32 reg; in ipu_di_data_wave_config() local
184 reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) | in ipu_di_data_wave_config()
186 __raw_writel(reg, DI_DW_GEN(di, wave_gen)); in ipu_di_data_wave_config()
192 u32 reg; in ipu_di_data_pin_config() local
194 reg = __raw_readl(DI_DW_GEN(di, wave_gen)); in ipu_di_data_pin_config()
195 reg &= ~(0x3 << (di_pin * 2)); in ipu_di_data_pin_config()
196 reg |= set << (di_pin * 2); in ipu_di_data_pin_config()
197 __raw_writel(reg, DI_DW_GEN(di, wave_gen)); in ipu_di_data_pin_config()
211 u32 reg; in ipu_di_sync_config() local
220 reg = (run_count << 19) | (++run_src << 16) | in ipu_di_sync_config()
[all …]
/openbmc/qemu/tests/qtest/
H A Driscv-iommu-test.c59 uint32_t reg; in test_reg_reset() local
64 reg = riscv_iommu_read_reg32(r_iommu, RISCV_IOMMU_REG_CQCSR); in test_reg_reset()
65 g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_CQEN, ==, 0); in test_reg_reset()
66 g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_CIE, ==, 0); in test_reg_reset()
67 g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_CQON, ==, 0); in test_reg_reset()
68 g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_BUSY, ==, 0); in test_reg_reset()
70 reg = riscv_iommu_read_reg32(r_iommu, RISCV_IOMMU_REG_FQCSR); in test_reg_reset()
71 g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_FQEN, ==, 0); in test_reg_reset()
72 g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_FIE, ==, 0); in test_reg_reset()
73 g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_FQON, ==, 0); in test_reg_reset()
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dmscc,luton.dtsi20 reg = <0>;
50 reg = <0x10100000 0x20>;
52 reg-io-width = <4>;
53 reg-shift = <2>;
60 reg = <0x70068 0x68>;
81 reg = <0x0070130 0x100>;
90 reg = <0x10000064 0x4>;
98 reg = <0x1e0000 0x0100>, // VTSS_TO_DEV_0
128 reg-names = "port0", "port1", "port2", "port3",
142 reg = <0>;
[all …]
/openbmc/qemu/target/xtensa/
H A Dgdbstub.c49 for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) { in xtensa_count_regs()
50 if (config->gdb_regmap.reg[i].type != xtRegisterTypeTieState && in xtensa_count_regs()
51 config->gdb_regmap.reg[i].type != xtRegisterTypeMapped && in xtensa_count_regs()
52 config->gdb_regmap.reg[i].type != xtRegisterTypeUnmapped) { in xtensa_count_regs()
55 if ((config->gdb_regmap.reg[i].flags & in xtensa_count_regs()
69 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; in xtensa_cpu_gdb_read_register() local
81 switch (reg->type) { in xtensa_cpu_gdb_read_register()
87 return gdb_get_reg32(mem_buf, env->phys_regs[(reg->targno & 0xff) in xtensa_cpu_gdb_read_register()
91 return gdb_get_reg32(mem_buf, env->sregs[reg->targno & 0xff]); in xtensa_cpu_gdb_read_register()
94 return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]); in xtensa_cpu_gdb_read_register()
[all …]
/openbmc/u-boot/board/aspeed/ast2600_dcscm/
H A Dast2600_dcscm.c75 u32 reg; in espi_init() local
78 reg = readl(SCU_BASE + 0x510); in espi_init()
79 if (reg & BIT(6)) in espi_init()
101 reg = readl(ESPI_BASE + 0x000); in espi_init()
102 reg |= 0xef; in espi_init()
103 writel(reg, ESPI_BASE + 0x000); in espi_init()
108 reg = readl(ESPI_BASE + 0x00c); in espi_init()
109 reg |= 0x80000000; in espi_init()
110 writel(reg, ESPI_BASE + 0x00c); in espi_init()
116 reg = readl(ESPI_BASE + 0x080); in espi_init()
[all …]
/openbmc/u-boot/arch/x86/cpu/quark/
H A Dmsg_port.c11 void msg_port_setup(int op, int port, int reg) in msg_port_setup() argument
15 (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE)); in msg_port_setup()
18 u32 msg_port_read(u8 port, u32 reg) in msg_port_read() argument
23 reg & 0xffffff00); in msg_port_read()
24 msg_port_setup(MSG_OP_READ, port, reg); in msg_port_read()
30 void msg_port_write(u8 port, u32 reg, u32 value) in msg_port_write() argument
34 reg & 0xffffff00); in msg_port_write()
35 msg_port_setup(MSG_OP_WRITE, port, reg); in msg_port_write()
38 u32 msg_port_alt_read(u8 port, u32 reg) in msg_port_alt_read() argument
43 reg & 0xffffff00); in msg_port_alt_read()
[all …]
/openbmc/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rv1108.c18 .reg = 0x418,
24 .reg = 0x418,
30 .reg = 0x418,
36 .reg = 0x418,
42 .reg = 0x418,
48 .reg = 0x418,
54 .reg = 0x418,
60 .reg = 0x418,
66 .reg = 0x41c,
72 .reg = 0x41c,
[all …]

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