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Searched refs:readw (Results 1 – 25 of 85) sorted by relevance

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/openbmc/u-boot/drivers/spi/
H A Dpl022_spi.c81 if ((readw(ps->base + SSP_PID0) == 0x22) && in pl022_is_supported()
82 (readw(ps->base + SSP_PID1) == 0x10) && in pl022_is_supported()
83 ((readw(ps->base + SSP_PID2) & 0xf) == 0x04) && in pl022_is_supported()
84 (readw(ps->base + SSP_PID3) == 0x00)) in pl022_is_supported()
112 while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) in flush()
113 readw(ps->base + SSP_DR); in flush()
114 } while (readw(ps->base + SSP_SR) & SSP_SR_MASK_BSY); in flush()
124 reg = readw(ps->base + SSP_CR1); in pl022_spi_claim_bus()
142 reg = readw(ps->base + SSP_CR1); in pl022_spi_release_bus()
180 if (readw(ps->base + SSP_SR) & SSP_SR_MASK_TNF) { in pl022_spi_xfer()
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/openbmc/u-boot/drivers/usb/musb/
H A Dmusb_udc.c116 w = readw(&musbr->ep[0].ep0.csr0); in musb_db_regs()
125 w = readw(&musbr->frame); in musb_db_regs()
131 w = readw(&musbr->ep[1].epN.rxmaxp); in musb_db_regs()
134 w = readw(&musbr->ep[1].epN.rxcsr); in musb_db_regs()
137 w = readw(&musbr->ep[1].epN.txmaxp); in musb_db_regs()
140 w = readw(&musbr->ep[1].epN.txcsr); in musb_db_regs()
158 readw(&musbr->intrrx); in musb_peri_softconnect()
159 readw(&musbr->intrtx); in musb_peri_softconnect()
209 csr0 = readw(&musbr->ep[0].ep0.csr0); in musb_peri_ep0_stall()
220 csr0 = readw(&musbr->ep[0].ep0.csr0); in musb_peri_ep0_ack_req()
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H A Dmusb_hcd.c43 csr = readw(&musbr->txcsr); in write_toggle()
58 csr = readw(&musbr->txcsr); in write_toggle()
65 csr = readw(&musbr->rxcsr); in write_toggle()
85 csr = readw(&musbr->txcsr); in check_stall()
93 csr = readw(&musbr->txcsr); in check_stall()
100 csr = readw(&musbr->rxcsr); in check_stall()
122 csr = readw(&musbr->txcsr); in wait_until_ep0_ready()
189 csr = readw(&musbr->txcsr); in wait_until_txep_ready()
221 csr = readw(&musbr->rxcsr); in wait_until_rxep_ready()
251 csr = readw(&musbr->txcsr); in ctrlreq_setup_phase()
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H A Dmusb_core.c82 csr = readw(&musbr->txcsr); in musb_configure_ep()
95 csr = readw(&musbr->rxcsr); in musb_configure_ep()
/openbmc/u-boot/board/ronetix/pm9263/
H A Dpm9263.c178 readw(PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
179 readw(PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
184 readw(PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
185 readw(PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
199 if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) { in pm9263_lcd_hw_psram_init()
204 readw(PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
205 readw(PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
213 if ((readw(PHYS_PSRAM) != 0x1234) in pm9263_lcd_hw_psram_init()
214 || (readw(PHYS_PSRAM + 2) != 0x5678)) in pm9263_lcd_hw_psram_init()
/openbmc/u-boot/drivers/w1/
H A Dmxc_w1.c68 if (!(readw(ctrl_addr) & mask)) in mxc_w1_touch_bit()
74 return (readw(ctrl_addr) & MXC_W1_CONTROL_RDST) ? 1 : 0; in mxc_w1_touch_bit()
93 readw(&regs->tx_rx); in mxc_w1_read_byte()
98 status = readw(&regs->interrupt); in mxc_w1_read_byte()
101 return (u8)readw(&regs->tx_rx); in mxc_w1_read_byte()
119 readw(&regs->tx_rx); in mxc_w1_write_byte()
124 status = readw(&regs->interrupt); in mxc_w1_write_byte()
136 reg_val = readw(&pdata->regs->control); in mxc_w1_reset()
/openbmc/u-boot/arch/sh/lib/
H A Dtime_sh2.c23 writew(readw(CMSTR) | 0x01, CMSTR); in cmt_timer_start()
28 writew(readw(CMSTR) & ~0x01, CMSTR); in cmt_timer_stop()
35 readw(CMCSR_0); in timer_init()
54 ulong data = readw(CMCNT_0); in get_usec()
H A Dtime.c32 writew(readw(TMU_BASE + TCR0) & ~TCR_TPSC, TMU_BASE + TCR0); in timer_init()
/openbmc/u-boot/board/compulab/common/
H A Domap3_smc911x.c38 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in cl_omap3_smc911x_setup_net_chip_gmpc()
41 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in cl_omap3_smc911x_setup_net_chip_gmpc()
44 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in cl_omap3_smc911x_setup_net_chip_gmpc()
/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Diobp.c35 u16 status = readw(RCB_REG(IOBPS)); in iobp_poll()
73 status = readw(RCB_REG(IOBPS)); in pch_iobp_trans_finish()
139 *resp = (readw(RCB_REG(IOBPS)) & IOBPS_TX_MASK) >> 1; in pch_iobp_exec()
/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dhelper.c64 tmp32 = (readw(pr_to32) & 0x0000ffff); in ddr_load_train_firmware()
66 tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); in ddr_load_train_firmware()
85 tmp32 = (readw(pr_to32) & 0x0000ffff); in ddr_load_train_firmware()
87 tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); in ddr_load_train_firmware()
/openbmc/u-boot/arch/microblaze/include/asm/
H A Dio.h27 #define readw(addr) \ macro
47 #define inw(addr) readw(addr)
55 #define in_be16(addr) readw(addr)
72 #define __raw_readw readw
/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_core.h119 reg_data = readw(addr); in reg_set_silent16()
129 debug("old value = %#06x ==> ", readw(addr)); in reg_set16()
131 debug("new value %#06x\n", readw(addr)); in reg_set16()
/openbmc/u-boot/board/isee/igep00x0/
H A Digep00x0.c120 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in setup_net_chip()
122 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in setup_net_chip()
124 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in setup_net_chip()
/openbmc/u-boot/arch/xtensa/include/asm/
H A Dio.h37 #define readw(addr) \ macro
46 #define __raw_readw readw
61 #define inw(port) readw((u16 *)((port)))
/openbmc/u-boot/include/
H A Diotrace.h54 #undef readw
55 #define readw(addr) iotrace_readw((const void *)(addr)) macro
H A Dwait_bit.h74 BUILD_WAIT_FOR_BIT(le16, u16, readw)
/openbmc/u-boot/board/ti/evm/
H A Devm.c248 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in setup_net_chip()
250 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in setup_net_chip()
252 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in setup_net_chip()
/openbmc/u-boot/drivers/mmc/
H A Dmv_sdhci.c53 writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata); in mv_sdhci_writeb()
55 writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata); in mv_sdhci_writeb()
H A Djz_mmc.c292 a = readw(priv->regs + MSC_RES); in jz_mmc_send_cmd()
294 b = readw(priv->regs + MSC_RES); in jz_mmc_send_cmd()
295 c = readw(priv->regs + MSC_RES); in jz_mmc_send_cmd()
301 cmd->response[0] = readw(priv->regs + MSC_RES) << 24; in jz_mmc_send_cmd()
302 cmd->response[0] |= readw(priv->regs + MSC_RES) << 8; in jz_mmc_send_cmd()
303 cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff; in jz_mmc_send_cmd()
/openbmc/u-boot/board/overo/
H A Dovero.c318 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in setup_net_chip()
320 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in setup_net_chip()
322 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in setup_net_chip()
/openbmc/qemu/tests/qtest/libqos/
H A Dsdhci.h41 uint16_t (*readw)(QSDHCI *s, uint32_t reg); member
H A Dsdhci.c70 sdhci->sdhci.readw = sdhci_mm_readw; in qos_init_sdhci_mm()
129 spci->sdhci.readw = sdhci_pci_readw; in sdhci_pci_create()
/openbmc/u-boot/include/linux/
H A Dio.h18 return readw(addr); in ioread16()
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Datmel_nand.c200 si[i] = readw(alpha_to + i * j) ^ si[i]; in pmecc_substitute()
210 tmp = readw(index_of + si[j]); in pmecc_substitute()
212 si[i] = readw(alpha_to + tmp); in pmecc_substitute()
344 a = readw(index_of + dmu[i]); in pmecc_get_sigma()
345 b = readw(index_of + dmu[ro]); in pmecc_get_sigma()
346 c = readw(index_of + smu[ro * num + k]); in pmecc_get_sigma()
348 a = readw(alpha_to + tmp % cw_len); in pmecc_get_sigma()
370 a = readw(index_of + in pmecc_get_sigma()
373 c = readw(index_of + b); in pmecc_get_sigma()
376 dmu[i + 1] = readw(alpha_to + tmp) ^ in pmecc_get_sigma()
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