1d7727139SPaul Burton // SPDX-License-Identifier: GPL-2.0+
2d7727139SPaul Burton /*
3d7727139SPaul Burton * Ingenic JZ MMC driver
4d7727139SPaul Burton *
5d7727139SPaul Burton * Copyright (c) 2013 Imagination Technologies
6d7727139SPaul Burton * Author: Paul Burton <paul.burton@imgtec.com>
7d7727139SPaul Burton */
8d7727139SPaul Burton
9d7727139SPaul Burton #include <common.h>
10d7727139SPaul Burton #include <malloc.h>
11d7727139SPaul Burton #include <mmc.h>
12d7727139SPaul Burton #include <asm/io.h>
13d7727139SPaul Burton #include <asm/unaligned.h>
14d7727139SPaul Burton #include <errno.h>
15d7727139SPaul Burton #include <mach/jz4780.h>
16d7727139SPaul Burton #include <wait_bit.h>
17d7727139SPaul Burton
18d7727139SPaul Burton /* Registers */
19d7727139SPaul Burton #define MSC_STRPCL 0x000
20d7727139SPaul Burton #define MSC_STAT 0x004
21d7727139SPaul Burton #define MSC_CLKRT 0x008
22d7727139SPaul Burton #define MSC_CMDAT 0x00c
23d7727139SPaul Burton #define MSC_RESTO 0x010
24d7727139SPaul Burton #define MSC_RDTO 0x014
25d7727139SPaul Burton #define MSC_BLKLEN 0x018
26d7727139SPaul Burton #define MSC_NOB 0x01c
27d7727139SPaul Burton #define MSC_SNOB 0x020
28d7727139SPaul Burton #define MSC_IMASK 0x024
29d7727139SPaul Burton #define MSC_IREG 0x028
30d7727139SPaul Burton #define MSC_CMD 0x02c
31d7727139SPaul Burton #define MSC_ARG 0x030
32d7727139SPaul Burton #define MSC_RES 0x034
33d7727139SPaul Burton #define MSC_RXFIFO 0x038
34d7727139SPaul Burton #define MSC_TXFIFO 0x03c
35d7727139SPaul Burton #define MSC_LPM 0x040
36d7727139SPaul Burton #define MSC_DMAC 0x044
37d7727139SPaul Burton #define MSC_DMANDA 0x048
38d7727139SPaul Burton #define MSC_DMADA 0x04c
39d7727139SPaul Burton #define MSC_DMALEN 0x050
40d7727139SPaul Burton #define MSC_DMACMD 0x054
41d7727139SPaul Burton #define MSC_CTRL2 0x058
42d7727139SPaul Burton #define MSC_RTCNT 0x05c
43d7727139SPaul Burton #define MSC_DBG 0x0fc
44d7727139SPaul Burton
45d7727139SPaul Burton /* MSC Clock and Control Register (MSC_STRPCL) */
46d7727139SPaul Burton #define MSC_STRPCL_EXIT_MULTIPLE BIT(7)
47d7727139SPaul Burton #define MSC_STRPCL_EXIT_TRANSFER BIT(6)
48d7727139SPaul Burton #define MSC_STRPCL_START_READWAIT BIT(5)
49d7727139SPaul Burton #define MSC_STRPCL_STOP_READWAIT BIT(4)
50d7727139SPaul Burton #define MSC_STRPCL_RESET BIT(3)
51d7727139SPaul Burton #define MSC_STRPCL_START_OP BIT(2)
52d7727139SPaul Burton #define MSC_STRPCL_CLOCK_CONTROL_STOP BIT(0)
53d7727139SPaul Burton #define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
54d7727139SPaul Burton
55d7727139SPaul Burton /* MSC Status Register (MSC_STAT) */
56d7727139SPaul Burton #define MSC_STAT_AUTO_CMD_DONE BIT(31)
57d7727139SPaul Burton #define MSC_STAT_IS_RESETTING BIT(15)
58d7727139SPaul Burton #define MSC_STAT_SDIO_INT_ACTIVE BIT(14)
59d7727139SPaul Burton #define MSC_STAT_PRG_DONE BIT(13)
60d7727139SPaul Burton #define MSC_STAT_DATA_TRAN_DONE BIT(12)
61d7727139SPaul Burton #define MSC_STAT_END_CMD_RES BIT(11)
62d7727139SPaul Burton #define MSC_STAT_DATA_FIFO_AFULL BIT(10)
63d7727139SPaul Burton #define MSC_STAT_IS_READWAIT BIT(9)
64d7727139SPaul Burton #define MSC_STAT_CLK_EN BIT(8)
65d7727139SPaul Burton #define MSC_STAT_DATA_FIFO_FULL BIT(7)
66d7727139SPaul Burton #define MSC_STAT_DATA_FIFO_EMPTY BIT(6)
67d7727139SPaul Burton #define MSC_STAT_CRC_RES_ERR BIT(5)
68d7727139SPaul Burton #define MSC_STAT_CRC_READ_ERROR BIT(4)
69d7727139SPaul Burton #define MSC_STAT_CRC_WRITE_ERROR BIT(2)
70d7727139SPaul Burton #define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
71d7727139SPaul Burton #define MSC_STAT_TIME_OUT_RES BIT(1)
72d7727139SPaul Burton #define MSC_STAT_TIME_OUT_READ BIT(0)
73d7727139SPaul Burton
74d7727139SPaul Burton /* MSC Bus Clock Control Register (MSC_CLKRT) */
75d7727139SPaul Burton #define MSC_CLKRT_CLK_RATE_MASK 0x7
76d7727139SPaul Burton
77d7727139SPaul Burton /* MSC Command Sequence Control Register (MSC_CMDAT) */
78d7727139SPaul Burton #define MSC_CMDAT_IO_ABORT BIT(11)
79d7727139SPaul Burton #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << 9)
80d7727139SPaul Burton #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << 9)
81d7727139SPaul Burton #define MSC_CMDAT_DMA_EN BIT(8)
82d7727139SPaul Burton #define MSC_CMDAT_INIT BIT(7)
83d7727139SPaul Burton #define MSC_CMDAT_BUSY BIT(6)
84d7727139SPaul Burton #define MSC_CMDAT_STREAM_BLOCK BIT(5)
85d7727139SPaul Burton #define MSC_CMDAT_WRITE BIT(4)
86d7727139SPaul Burton #define MSC_CMDAT_DATA_EN BIT(3)
87d7727139SPaul Burton #define MSC_CMDAT_RESPONSE_MASK (0x7 << 0)
88d7727139SPaul Burton #define MSC_CMDAT_RESPONSE_NONE (0x0 << 0) /* No response */
89d7727139SPaul Burton #define MSC_CMDAT_RESPONSE_R1 (0x1 << 0) /* Format R1 and R1b */
90d7727139SPaul Burton #define MSC_CMDAT_RESPONSE_R2 (0x2 << 0) /* Format R2 */
91d7727139SPaul Burton #define MSC_CMDAT_RESPONSE_R3 (0x3 << 0) /* Format R3 */
92d7727139SPaul Burton #define MSC_CMDAT_RESPONSE_R4 (0x4 << 0) /* Format R4 */
93d7727139SPaul Burton #define MSC_CMDAT_RESPONSE_R5 (0x5 << 0) /* Format R5 */
94d7727139SPaul Burton #define MSC_CMDAT_RESPONSE_R6 (0x6 << 0) /* Format R6 */
95d7727139SPaul Burton
96d7727139SPaul Burton /* MSC Interrupts Mask Register (MSC_IMASK) */
97d7727139SPaul Burton #define MSC_IMASK_TIME_OUT_RES BIT(9)
98d7727139SPaul Burton #define MSC_IMASK_TIME_OUT_READ BIT(8)
99d7727139SPaul Burton #define MSC_IMASK_SDIO BIT(7)
100d7727139SPaul Burton #define MSC_IMASK_TXFIFO_WR_REQ BIT(6)
101d7727139SPaul Burton #define MSC_IMASK_RXFIFO_RD_REQ BIT(5)
102d7727139SPaul Burton #define MSC_IMASK_END_CMD_RES BIT(2)
103d7727139SPaul Burton #define MSC_IMASK_PRG_DONE BIT(1)
104d7727139SPaul Burton #define MSC_IMASK_DATA_TRAN_DONE BIT(0)
105d7727139SPaul Burton
106d7727139SPaul Burton /* MSC Interrupts Status Register (MSC_IREG) */
107d7727139SPaul Burton #define MSC_IREG_TIME_OUT_RES BIT(9)
108d7727139SPaul Burton #define MSC_IREG_TIME_OUT_READ BIT(8)
109d7727139SPaul Burton #define MSC_IREG_SDIO BIT(7)
110d7727139SPaul Burton #define MSC_IREG_TXFIFO_WR_REQ BIT(6)
111d7727139SPaul Burton #define MSC_IREG_RXFIFO_RD_REQ BIT(5)
112d7727139SPaul Burton #define MSC_IREG_END_CMD_RES BIT(2)
113d7727139SPaul Burton #define MSC_IREG_PRG_DONE BIT(1)
114d7727139SPaul Burton #define MSC_IREG_DATA_TRAN_DONE BIT(0)
115d7727139SPaul Burton
116d7727139SPaul Burton struct jz_mmc_plat {
117d7727139SPaul Burton struct mmc_config cfg;
118d7727139SPaul Burton struct mmc mmc;
119d7727139SPaul Burton };
120d7727139SPaul Burton
121d7727139SPaul Burton struct jz_mmc_priv {
122d7727139SPaul Burton void __iomem *regs;
123d7727139SPaul Burton u32 flags;
124d7727139SPaul Burton /* priv flags */
125d7727139SPaul Burton #define JZ_MMC_BUS_WIDTH_MASK 0x3
126d7727139SPaul Burton #define JZ_MMC_BUS_WIDTH_1 0x0
127d7727139SPaul Burton #define JZ_MMC_BUS_WIDTH_4 0x2
128d7727139SPaul Burton #define JZ_MMC_BUS_WIDTH_8 0x3
129d7727139SPaul Burton #define JZ_MMC_SENT_INIT BIT(2)
130d7727139SPaul Burton };
131d7727139SPaul Burton
jz_mmc_clock_rate(void)132d7727139SPaul Burton static int jz_mmc_clock_rate(void)
133d7727139SPaul Burton {
134d7727139SPaul Burton return 24000000;
135d7727139SPaul Burton }
136d7727139SPaul Burton
137*82d54647SEzequiel Garcia #if CONFIG_IS_ENABLED(MMC_WRITE)
jz_mmc_write_data(struct jz_mmc_priv * priv,struct mmc_data * data)138*82d54647SEzequiel Garcia static inline void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
139*82d54647SEzequiel Garcia {
140*82d54647SEzequiel Garcia int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
141*82d54647SEzequiel Garcia const void *buf = data->src;
142*82d54647SEzequiel Garcia
143*82d54647SEzequiel Garcia while (sz--) {
144*82d54647SEzequiel Garcia u32 val = get_unaligned_le32(buf);
145*82d54647SEzequiel Garcia
146*82d54647SEzequiel Garcia wait_for_bit_le32(priv->regs + MSC_IREG,
147*82d54647SEzequiel Garcia MSC_IREG_TXFIFO_WR_REQ,
148*82d54647SEzequiel Garcia true, 10000, false);
149*82d54647SEzequiel Garcia writel(val, priv->regs + MSC_TXFIFO);
150*82d54647SEzequiel Garcia buf += 4;
151*82d54647SEzequiel Garcia }
152*82d54647SEzequiel Garcia }
153*82d54647SEzequiel Garcia #else
jz_mmc_write_data(struct jz_mmc_priv * priv,struct mmc_data * data)154*82d54647SEzequiel Garcia static void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
155*82d54647SEzequiel Garcia {}
156*82d54647SEzequiel Garcia #endif
157*82d54647SEzequiel Garcia
jz_mmc_read_data(struct jz_mmc_priv * priv,struct mmc_data * data)158*82d54647SEzequiel Garcia static inline int jz_mmc_read_data(struct jz_mmc_priv *priv, struct mmc_data *data)
159*82d54647SEzequiel Garcia {
160*82d54647SEzequiel Garcia int sz = data->blocks * data->blocksize;
161*82d54647SEzequiel Garcia void *buf = data->dest;
162*82d54647SEzequiel Garcia u32 stat, val;
163*82d54647SEzequiel Garcia
164*82d54647SEzequiel Garcia do {
165*82d54647SEzequiel Garcia stat = readl(priv->regs + MSC_STAT);
166*82d54647SEzequiel Garcia
167*82d54647SEzequiel Garcia if (stat & MSC_STAT_TIME_OUT_READ)
168*82d54647SEzequiel Garcia return -ETIMEDOUT;
169*82d54647SEzequiel Garcia if (stat & MSC_STAT_CRC_READ_ERROR)
170*82d54647SEzequiel Garcia return -EINVAL;
171*82d54647SEzequiel Garcia if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
172*82d54647SEzequiel Garcia udelay(10);
173*82d54647SEzequiel Garcia continue;
174*82d54647SEzequiel Garcia }
175*82d54647SEzequiel Garcia do {
176*82d54647SEzequiel Garcia val = readl(priv->regs + MSC_RXFIFO);
177*82d54647SEzequiel Garcia if (sz == 1)
178*82d54647SEzequiel Garcia *(u8 *)buf = (u8)val;
179*82d54647SEzequiel Garcia else if (sz == 2)
180*82d54647SEzequiel Garcia put_unaligned_le16(val, buf);
181*82d54647SEzequiel Garcia else if (sz >= 4)
182*82d54647SEzequiel Garcia put_unaligned_le32(val, buf);
183*82d54647SEzequiel Garcia buf += 4;
184*82d54647SEzequiel Garcia sz -= 4;
185*82d54647SEzequiel Garcia stat = readl(priv->regs + MSC_STAT);
186*82d54647SEzequiel Garcia } while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
187*82d54647SEzequiel Garcia } while (!(stat & MSC_STAT_DATA_TRAN_DONE));
188*82d54647SEzequiel Garcia return 0;
189*82d54647SEzequiel Garcia }
190*82d54647SEzequiel Garcia
jz_mmc_send_cmd(struct mmc * mmc,struct jz_mmc_priv * priv,struct mmc_cmd * cmd,struct mmc_data * data)191d7727139SPaul Burton static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv,
192d7727139SPaul Burton struct mmc_cmd *cmd, struct mmc_data *data)
193d7727139SPaul Burton {
194d7727139SPaul Burton u32 stat, mask, cmdat = 0;
195d7727139SPaul Burton int i, ret;
196d7727139SPaul Burton
197d7727139SPaul Burton /* stop the clock */
198d7727139SPaul Burton writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL);
199d7727139SPaul Burton ret = wait_for_bit_le32(priv->regs + MSC_STAT,
200d7727139SPaul Burton MSC_STAT_CLK_EN, false, 10000, false);
201d7727139SPaul Burton if (ret)
202d7727139SPaul Burton return ret;
203d7727139SPaul Burton
204d7727139SPaul Burton writel(0, priv->regs + MSC_DMAC);
205d7727139SPaul Burton
206d7727139SPaul Burton /* setup command */
207d7727139SPaul Burton writel(cmd->cmdidx, priv->regs + MSC_CMD);
208d7727139SPaul Burton writel(cmd->cmdarg, priv->regs + MSC_ARG);
209d7727139SPaul Burton
210d7727139SPaul Burton if (data) {
211d7727139SPaul Burton /* setup data */
212d7727139SPaul Burton cmdat |= MSC_CMDAT_DATA_EN;
213d7727139SPaul Burton if (data->flags & MMC_DATA_WRITE)
214d7727139SPaul Burton cmdat |= MSC_CMDAT_WRITE;
215d7727139SPaul Burton
216d7727139SPaul Burton writel(data->blocks, priv->regs + MSC_NOB);
217d7727139SPaul Burton writel(data->blocksize, priv->regs + MSC_BLKLEN);
218d7727139SPaul Burton } else {
219d7727139SPaul Burton writel(0, priv->regs + MSC_NOB);
220d7727139SPaul Burton writel(0, priv->regs + MSC_BLKLEN);
221d7727139SPaul Burton }
222d7727139SPaul Burton
223d7727139SPaul Burton /* setup response */
224d7727139SPaul Burton switch (cmd->resp_type) {
225d7727139SPaul Burton case MMC_RSP_NONE:
226d7727139SPaul Burton break;
227d7727139SPaul Burton case MMC_RSP_R1:
228d7727139SPaul Burton case MMC_RSP_R1b:
229d7727139SPaul Burton cmdat |= MSC_CMDAT_RESPONSE_R1;
230d7727139SPaul Burton break;
231d7727139SPaul Burton case MMC_RSP_R2:
232d7727139SPaul Burton cmdat |= MSC_CMDAT_RESPONSE_R2;
233d7727139SPaul Burton break;
234d7727139SPaul Burton case MMC_RSP_R3:
235d7727139SPaul Burton cmdat |= MSC_CMDAT_RESPONSE_R3;
236d7727139SPaul Burton break;
237d7727139SPaul Burton default:
238d7727139SPaul Burton break;
239d7727139SPaul Burton }
240d7727139SPaul Burton
241d7727139SPaul Burton if (cmd->resp_type & MMC_RSP_BUSY)
242d7727139SPaul Burton cmdat |= MSC_CMDAT_BUSY;
243d7727139SPaul Burton
244d7727139SPaul Burton /* set init for the first command only */
245d7727139SPaul Burton if (!(priv->flags & JZ_MMC_SENT_INIT)) {
246d7727139SPaul Burton cmdat |= MSC_CMDAT_INIT;
247d7727139SPaul Burton priv->flags |= JZ_MMC_SENT_INIT;
248d7727139SPaul Burton }
249d7727139SPaul Burton
250d7727139SPaul Burton cmdat |= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9;
251d7727139SPaul Burton
252d7727139SPaul Burton /* write the data setup */
253d7727139SPaul Burton writel(cmdat, priv->regs + MSC_CMDAT);
254d7727139SPaul Burton
255d7727139SPaul Burton /* unmask interrupts */
256d7727139SPaul Burton mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_TIME_OUT_RES);
257d7727139SPaul Burton if (data) {
258d7727139SPaul Burton mask &= ~MSC_IMASK_DATA_TRAN_DONE;
259d7727139SPaul Burton if (data->flags & MMC_DATA_WRITE) {
260d7727139SPaul Burton mask &= ~MSC_IMASK_TXFIFO_WR_REQ;
261d7727139SPaul Burton } else {
262d7727139SPaul Burton mask &= ~(MSC_IMASK_RXFIFO_RD_REQ |
263d7727139SPaul Burton MSC_IMASK_TIME_OUT_READ);
264d7727139SPaul Burton }
265d7727139SPaul Burton }
266d7727139SPaul Burton writel(mask, priv->regs + MSC_IMASK);
267d7727139SPaul Burton
268d7727139SPaul Burton /* clear interrupts */
269d7727139SPaul Burton writel(0xffffffff, priv->regs + MSC_IREG);
270d7727139SPaul Burton
271d7727139SPaul Burton /* start the command (& the clock) */
272d7727139SPaul Burton writel(MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START,
273d7727139SPaul Burton priv->regs + MSC_STRPCL);
274d7727139SPaul Burton
275d7727139SPaul Burton /* wait for completion */
276d7727139SPaul Burton for (i = 0; i < 100; i++) {
277d7727139SPaul Burton stat = readl(priv->regs + MSC_IREG);
278d7727139SPaul Burton stat &= MSC_IREG_END_CMD_RES | MSC_IREG_TIME_OUT_RES;
279d7727139SPaul Burton if (stat)
280d7727139SPaul Burton break;
281d7727139SPaul Burton mdelay(1);
282d7727139SPaul Burton }
283d7727139SPaul Burton writel(stat, priv->regs + MSC_IREG);
284d7727139SPaul Burton if (stat & MSC_IREG_TIME_OUT_RES)
285d7727139SPaul Burton return -ETIMEDOUT;
286d7727139SPaul Burton
287d7727139SPaul Burton if (cmd->resp_type & MMC_RSP_PRESENT) {
288d7727139SPaul Burton /* read the response */
289d7727139SPaul Burton if (cmd->resp_type & MMC_RSP_136) {
290d7727139SPaul Burton u16 a, b, c, i;
291d7727139SPaul Burton
292d7727139SPaul Burton a = readw(priv->regs + MSC_RES);
293d7727139SPaul Burton for (i = 0; i < 4; i++) {
294d7727139SPaul Burton b = readw(priv->regs + MSC_RES);
295d7727139SPaul Burton c = readw(priv->regs + MSC_RES);
296d7727139SPaul Burton cmd->response[i] =
297d7727139SPaul Burton (a << 24) | (b << 8) | (c >> 8);
298d7727139SPaul Burton a = c;
299d7727139SPaul Burton }
300d7727139SPaul Burton } else {
301d7727139SPaul Burton cmd->response[0] = readw(priv->regs + MSC_RES) << 24;
302d7727139SPaul Burton cmd->response[0] |= readw(priv->regs + MSC_RES) << 8;
303d7727139SPaul Burton cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff;
304d7727139SPaul Burton }
305d7727139SPaul Burton }
306*82d54647SEzequiel Garcia if (data) {
307*82d54647SEzequiel Garcia if (data->flags & MMC_DATA_WRITE)
308*82d54647SEzequiel Garcia jz_mmc_write_data(priv, data);
309*82d54647SEzequiel Garcia else if (data->flags & MMC_DATA_READ) {
310*82d54647SEzequiel Garcia ret = jz_mmc_read_data(priv, data);
311*82d54647SEzequiel Garcia if (ret)
312*82d54647SEzequiel Garcia return ret;
313d7727139SPaul Burton }
314d7727139SPaul Burton }
315d7727139SPaul Burton
316d7727139SPaul Burton return 0;
317d7727139SPaul Burton }
318d7727139SPaul Burton
jz_mmc_set_ios(struct mmc * mmc,struct jz_mmc_priv * priv)319d7727139SPaul Burton static int jz_mmc_set_ios(struct mmc *mmc, struct jz_mmc_priv *priv)
320d7727139SPaul Burton {
321d7727139SPaul Burton u32 real_rate = jz_mmc_clock_rate();
322d7727139SPaul Burton u8 clk_div = 0;
323d7727139SPaul Burton
324d7727139SPaul Burton /* calculate clock divide */
325d7727139SPaul Burton while ((real_rate > mmc->clock) && (clk_div < 7)) {
326d7727139SPaul Burton real_rate >>= 1;
327d7727139SPaul Burton clk_div++;
328d7727139SPaul Burton }
329d7727139SPaul Burton writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT);
330d7727139SPaul Burton
331d7727139SPaul Burton /* set the bus width for the next command */
332d7727139SPaul Burton priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK;
333d7727139SPaul Burton if (mmc->bus_width == 8)
334d7727139SPaul Burton priv->flags |= JZ_MMC_BUS_WIDTH_8;
335d7727139SPaul Burton else if (mmc->bus_width == 4)
336d7727139SPaul Burton priv->flags |= JZ_MMC_BUS_WIDTH_4;
337d7727139SPaul Burton else
338d7727139SPaul Burton priv->flags |= JZ_MMC_BUS_WIDTH_1;
339d7727139SPaul Burton
340d7727139SPaul Burton return 0;
341d7727139SPaul Burton }
342d7727139SPaul Burton
jz_mmc_core_init(struct mmc * mmc)343d7727139SPaul Burton static int jz_mmc_core_init(struct mmc *mmc)
344d7727139SPaul Burton {
345d7727139SPaul Burton struct jz_mmc_priv *priv = mmc->priv;
346d7727139SPaul Burton int ret;
347d7727139SPaul Burton
348d7727139SPaul Burton /* Reset */
349d7727139SPaul Burton writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL);
350d7727139SPaul Burton ret = wait_for_bit_le32(priv->regs + MSC_STAT,
351d7727139SPaul Burton MSC_STAT_IS_RESETTING, false, 10000, false);
352d7727139SPaul Burton if (ret)
353d7727139SPaul Burton return ret;
354d7727139SPaul Burton
355d7727139SPaul Burton /* Maximum timeouts */
356d7727139SPaul Burton writel(0xffff, priv->regs + MSC_RESTO);
357d7727139SPaul Burton writel(0xffffffff, priv->regs + MSC_RDTO);
358d7727139SPaul Burton
359d7727139SPaul Burton /* Enable low power mode */
360d7727139SPaul Burton writel(0x1, priv->regs + MSC_LPM);
361d7727139SPaul Burton
362d7727139SPaul Burton return 0;
363d7727139SPaul Burton }
364d7727139SPaul Burton
365d7727139SPaul Burton #if !CONFIG_IS_ENABLED(DM_MMC)
366d7727139SPaul Burton
jz_mmc_legacy_send_cmd(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)367d7727139SPaul Burton static int jz_mmc_legacy_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
368d7727139SPaul Burton struct mmc_data *data)
369d7727139SPaul Burton {
370d7727139SPaul Burton struct jz_mmc_priv *priv = mmc->priv;
371d7727139SPaul Burton
372d7727139SPaul Burton return jz_mmc_send_cmd(mmc, priv, cmd, data);
373d7727139SPaul Burton }
374d7727139SPaul Burton
jz_mmc_legacy_set_ios(struct mmc * mmc)375d7727139SPaul Burton static int jz_mmc_legacy_set_ios(struct mmc *mmc)
376d7727139SPaul Burton {
377d7727139SPaul Burton struct jz_mmc_priv *priv = mmc->priv;
378d7727139SPaul Burton
379d7727139SPaul Burton return jz_mmc_set_ios(mmc, priv);
380d7727139SPaul Burton };
381d7727139SPaul Burton
382d7727139SPaul Burton static const struct mmc_ops jz_msc_ops = {
383d7727139SPaul Burton .send_cmd = jz_mmc_legacy_send_cmd,
384d7727139SPaul Burton .set_ios = jz_mmc_legacy_set_ios,
385d7727139SPaul Burton .init = jz_mmc_core_init,
386d7727139SPaul Burton };
387d7727139SPaul Burton
388d7727139SPaul Burton static struct jz_mmc_priv jz_mmc_priv_static;
389d7727139SPaul Burton static struct jz_mmc_plat jz_mmc_plat_static = {
390d7727139SPaul Burton .cfg = {
391d7727139SPaul Burton .name = "MSC",
392d7727139SPaul Burton .ops = &jz_msc_ops,
393d7727139SPaul Burton
394d7727139SPaul Burton .voltages = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
395d7727139SPaul Burton MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
396d7727139SPaul Burton MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36,
397d7727139SPaul Burton .host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,
398d7727139SPaul Burton
399d7727139SPaul Burton .f_min = 375000,
400d7727139SPaul Burton .f_max = 48000000,
401d7727139SPaul Burton .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
402d7727139SPaul Burton },
403d7727139SPaul Burton };
404d7727139SPaul Burton
jz_mmc_init(void __iomem * base)405d7727139SPaul Burton int jz_mmc_init(void __iomem *base)
406d7727139SPaul Burton {
407d7727139SPaul Burton struct mmc *mmc;
408d7727139SPaul Burton
409d7727139SPaul Burton jz_mmc_priv_static.regs = base;
410d7727139SPaul Burton
411d7727139SPaul Burton mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static);
412d7727139SPaul Burton
413d7727139SPaul Burton return mmc ? 0 : -ENODEV;
414d7727139SPaul Burton }
415d7727139SPaul Burton
416d7727139SPaul Burton #else /* CONFIG_DM_MMC */
417d7727139SPaul Burton
418d7727139SPaul Burton #include <dm.h>
419d7727139SPaul Burton DECLARE_GLOBAL_DATA_PTR;
420d7727139SPaul Burton
jz_mmc_dm_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)421d7727139SPaul Burton static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
422d7727139SPaul Burton struct mmc_data *data)
423d7727139SPaul Burton {
424d7727139SPaul Burton struct jz_mmc_priv *priv = dev_get_priv(dev);
425d7727139SPaul Burton struct mmc *mmc = mmc_get_mmc_dev(dev);
426d7727139SPaul Burton
427d7727139SPaul Burton return jz_mmc_send_cmd(mmc, priv, cmd, data);
428d7727139SPaul Burton }
429d7727139SPaul Burton
jz_mmc_dm_set_ios(struct udevice * dev)430d7727139SPaul Burton static int jz_mmc_dm_set_ios(struct udevice *dev)
431d7727139SPaul Burton {
432d7727139SPaul Burton struct jz_mmc_priv *priv = dev_get_priv(dev);
433d7727139SPaul Burton struct mmc *mmc = mmc_get_mmc_dev(dev);
434d7727139SPaul Burton
435d7727139SPaul Burton return jz_mmc_set_ios(mmc, priv);
436d7727139SPaul Burton };
437d7727139SPaul Burton
438d7727139SPaul Burton static const struct dm_mmc_ops jz_msc_ops = {
439d7727139SPaul Burton .send_cmd = jz_mmc_dm_send_cmd,
440d7727139SPaul Burton .set_ios = jz_mmc_dm_set_ios,
441d7727139SPaul Burton };
442d7727139SPaul Burton
jz_mmc_ofdata_to_platdata(struct udevice * dev)443d7727139SPaul Burton static int jz_mmc_ofdata_to_platdata(struct udevice *dev)
444d7727139SPaul Burton {
445d7727139SPaul Burton struct jz_mmc_priv *priv = dev_get_priv(dev);
446d7727139SPaul Burton struct jz_mmc_plat *plat = dev_get_platdata(dev);
447d7727139SPaul Burton struct mmc_config *cfg;
448d7727139SPaul Burton int ret;
449d7727139SPaul Burton
450d7727139SPaul Burton priv->regs = map_physmem(devfdt_get_addr(dev), 0x100, MAP_NOCACHE);
451d7727139SPaul Burton cfg = &plat->cfg;
452d7727139SPaul Burton
453d7727139SPaul Burton cfg->name = "MSC";
454d7727139SPaul Burton cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
455d7727139SPaul Burton
456d7727139SPaul Burton ret = mmc_of_parse(dev, cfg);
457d7727139SPaul Burton if (ret < 0) {
458d7727139SPaul Burton dev_err(dev, "failed to parse host caps\n");
459d7727139SPaul Burton return ret;
460d7727139SPaul Burton }
461d7727139SPaul Burton
462d7727139SPaul Burton cfg->f_min = 400000;
463d7727139SPaul Burton cfg->f_max = 52000000;
464d7727139SPaul Burton
465d7727139SPaul Burton cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
466d7727139SPaul Burton cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
467d7727139SPaul Burton
468d7727139SPaul Burton return 0;
469d7727139SPaul Burton }
470d7727139SPaul Burton
jz_mmc_bind(struct udevice * dev)471d7727139SPaul Burton static int jz_mmc_bind(struct udevice *dev)
472d7727139SPaul Burton {
473d7727139SPaul Burton struct jz_mmc_plat *plat = dev_get_platdata(dev);
474d7727139SPaul Burton
475d7727139SPaul Burton return mmc_bind(dev, &plat->mmc, &plat->cfg);
476d7727139SPaul Burton }
477d7727139SPaul Burton
jz_mmc_probe(struct udevice * dev)478d7727139SPaul Burton static int jz_mmc_probe(struct udevice *dev)
479d7727139SPaul Burton {
480d7727139SPaul Burton struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
481d7727139SPaul Burton struct jz_mmc_priv *priv = dev_get_priv(dev);
482d7727139SPaul Burton struct jz_mmc_plat *plat = dev_get_platdata(dev);
483d7727139SPaul Burton
484d7727139SPaul Burton plat->mmc.priv = priv;
485d7727139SPaul Burton upriv->mmc = &plat->mmc;
486d7727139SPaul Burton return jz_mmc_core_init(&plat->mmc);
487d7727139SPaul Burton }
488d7727139SPaul Burton
489d7727139SPaul Burton static const struct udevice_id jz_mmc_ids[] = {
490d7727139SPaul Burton { .compatible = "ingenic,jz4780-mmc" },
491d7727139SPaul Burton { }
492d7727139SPaul Burton };
493d7727139SPaul Burton
494d7727139SPaul Burton U_BOOT_DRIVER(jz_mmc_drv) = {
495d7727139SPaul Burton .name = "jz_mmc",
496d7727139SPaul Burton .id = UCLASS_MMC,
497d7727139SPaul Burton .of_match = jz_mmc_ids,
498d7727139SPaul Burton .ofdata_to_platdata = jz_mmc_ofdata_to_platdata,
499d7727139SPaul Burton .bind = jz_mmc_bind,
500d7727139SPaul Burton .probe = jz_mmc_probe,
501d7727139SPaul Burton .priv_auto_alloc_size = sizeof(struct jz_mmc_priv),
502d7727139SPaul Burton .platdata_auto_alloc_size = sizeof(struct jz_mmc_plat),
503d7727139SPaul Burton .ops = &jz_msc_ops,
504d7727139SPaul Burton };
505d7727139SPaul Burton #endif /* CONFIG_DM_MMC */
506