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Searched refs:rbar (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/vfio/pci/
H A Dvfio_pci_config.c423 u32 *rbar = vdev->rbar; in vfio_bar_restore() local
432 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++) in vfio_bar_restore()
433 pci_user_write_config_dword(pdev, i, *rbar); in vfio_bar_restore()
435 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar); in vfio_bar_restore()
549 if (vdev->rbar[i]) { in vfio_need_bar_restore()
551 if (ret || vdev->rbar[i] != bar) in vfio_need_bar_restore()
1770 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]); in vfio_config_init()
1771 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]); in vfio_config_init()
1772 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]); in vfio_config_init()
1773 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]); in vfio_config_init()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7m/
H A Dmpu.c39 &V7M_MPU->rbar); in mpu_config()
/openbmc/u-boot/arch/arm/include/asm/
H A Darmv7m.h62 uint32_t rbar; /* Region Base Address Register */ member
/openbmc/linux/include/linux/
H A Dvfio_pci_core.h70 u32 rbar[7]; member
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/
H A D0001-platform-corstone1000-Update-MPU-configuration.patch170 uint32_t rbar; /* region base address register */
194 rbar = base & MPU_RBAR_ADDR_Msk;
196 ARM_MPU_SetRegionEx(rnr, rbar, rasr);
/openbmc/qemu/target/arm/
H A Dcpu.c497 memset(env->pmsav8.rbar[M_REG_NS], 0, in arm_cpu_reset_hold()
498 sizeof(*env->pmsav8.rbar[M_REG_NS]) in arm_cpu_reset_hold()
504 memset(env->pmsav8.rbar[M_REG_S], 0, in arm_cpu_reset_hold()
505 sizeof(*env->pmsav8.rbar[M_REG_S]) in arm_cpu_reset_hold()
538 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); in arm_cpu_reset_hold()
2468 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); in arm_cpu_realizefn()
2471 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); in arm_cpu_realizefn()
2504 env->sau.rbar = g_new0(uint32_t, nr); in arm_cpu_realizefn()
H A Dmachine.c659 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion,
711 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion,
723 VMSTATE_VARRAY_UINT32(env.sau.rbar, ARMCPU, sau_sregion, 0,
H A Dcpu.h752 uint32_t *rbar[M_REG_NUM_BANKS]; member
763 uint32_t *rbar; member
H A Dptw.c2559 return env->pmsav8.rbar[secure]; in regime_rbar()
2830 uint32_t base = env->sau.rbar[r] & ~0x1f; in v8m_security_lookup()
H A Dhelper.c4041 env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; in prbar_write()
4046 return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; in prbar_read()
4184 env->pmsav8.rbar[M_REG_NS][index] = value; in pmsav8r_regn_write()
4211 return env->pmsav8.rbar[M_REG_NS][index]; in pmsav8r_regn_read()
/openbmc/qemu/hw/intc/
H A Darmv7m_nvic.c1381 return cpu->env.pmsav8.rbar[attrs.secure][region]; in nvic_readl()
1464 return cpu->env.sau.rbar[region]; in nvic_readl()
1874 cpu->env.pmsav8.rbar[attrs.secure][region] = value; in nvic_writel()
2004 cpu->env.sau.rbar[region] = value & ~0x1f; in nvic_writel()