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Searched refs:rFPGA0_XA_HSSIParameter2 (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A Drtl8723b_phycfg.c113 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord); in phy_RFSerialRead_8723B()
115 …PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge… in phy_RFSerialRead_8723B()
122 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord); in phy_RFSerialRead_8723B()
123 …PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEd… in phy_RFSerialRead_8723B()
124 …PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge… in phy_RFSerialRead_8723B()
325 …pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2… in phy_InitBBRFRegisterDefinition()
/openbmc/linux/drivers/staging/rtl8192u/
H A Dr819xU_phyreg.h11 #define rFPGA0_XA_HSSIParameter2 0x824 macro
H A Dr819xU_phy.c615 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; in rtl8192_InitBBRFRegDef()
816 rFPGA0_XA_HSSIParameter2, in rtl8192_BB_Config_ParaFile()
/openbmc/linux/drivers/staging/rtl8712/
H A Drtl871x_mp.c423 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); in r8712_SwitchAntenna()
430 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1); in r8712_SwitchAntenna()
437 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); in r8712_SwitchAntenna()
H A Drtl871x_mp_phy_regdef.h93 #define rFPGA0_XA_HSSIParameter2 0x824 macro
/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h50 #define rFPGA0_XA_HSSIParameter2 0x824 macro
H A Dr8192E_phy.c316 priv->phy_reg_def[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; in _rtl92e_init_bb_rf_reg_def()
H A Dr8192E_dev.c1247 rFPGA0_XA_HSSIParameter2, in _rtl92e_query_rxphystatus()
/openbmc/linux/drivers/staging/rtl8723bs/include/
H A DHal8192CPhyReg.h103 #define rFPGA0_XA_HSSIParameter2 0x824 macro