Home
last modified time | relevance | path

Searched refs:qemu_log_mask (Results 1 – 25 of 524) sorted by relevance

12345678910>>...21

/openbmc/qemu/hw/nvram/
H A Dbcm2835_otp.c40 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
44 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
48 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
52 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
56 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
60 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
64 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
68 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
72 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
76 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
[all …]
/openbmc/qemu/hw/ssi/
H A Dstm32f2xx_spi.c79 qemu_log_mask(LOG_UNIMP, "%s: Interrupts and DMA are not implemented\n", in stm32f2xx_spi_read()
89 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \ in stm32f2xx_spi_read()
93 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \ in stm32f2xx_spi_read()
97 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \ in stm32f2xx_spi_read()
101 qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \ in stm32f2xx_spi_read()
105 qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \ in stm32f2xx_spi_read()
109 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", in stm32f2xx_spi_read()
129 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_spi_write()
143 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented\n", __func__); in stm32f2xx_spi_write()
146 qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \ in stm32f2xx_spi_write()
[all …]
/openbmc/qemu/target/microblaze/
H A Dmmu.c65 qemu_log_mask(LOG_GUEST_ERROR, "Illegal rpid=%x\n", newpid); in mmu_change_pid()
96 qemu_log_mask(LOG_UNIMP, "%d pages not supported\n", tlb_size); in mmu_translate()
121 qemu_log_mask(LOG_GUEST_ERROR, in mmu_translate()
172 qemu_log_mask(CPU_LOG_MMU, in mmu_translate()
186 qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n"); in mmu_read()
190 qemu_log_mask(LOG_GUEST_ERROR, "Extended access only to TLBLO.\n"); in mmu_read()
199 qemu_log_mask(LOG_GUEST_ERROR, in mmu_read()
212 qemu_log_mask(LOG_GUEST_ERROR, in mmu_read()
222 qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n"); in mmu_read()
225 qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn); in mmu_read()
[all …]
H A Dhelper.c66 qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n", in mb_cpu_tlb_fill()
78 qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n", in mb_cpu_tlb_fill()
121 qemu_log_mask(LOG_GUEST_ERROR, in mb_cpu_do_interrupt()
126 qemu_log_mask(CPU_LOG_INT, in mb_cpu_do_interrupt()
145 qemu_log_mask(CPU_LOG_INT, in mb_cpu_do_interrupt()
175 qemu_log_mask(CPU_LOG_INT, in mb_cpu_do_interrupt()
189 qemu_log_mask(CPU_LOG_INT, in mb_cpu_do_interrupt()
215 qemu_log_mask(CPU_LOG_INT, in mb_cpu_do_interrupt()
218 qemu_log_mask(CPU_LOG_INT, in mb_cpu_do_interrupt()
222 qemu_log_mask(CPU_LOG_INT, in mb_cpu_do_interrupt()
[all …]
/openbmc/qemu/hw/char/
H A Dbcm2835_aux.c112 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__); in bcm2835_aux_read()
116 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__); in bcm2835_aux_read()
127 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MSR_REG unsupported\n", __func__); in bcm2835_aux_read()
131 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__); in bcm2835_aux_read()
147 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__); in bcm2835_aux_read()
151 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", in bcm2835_aux_read()
166 qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI" in bcm2835_aux_write()
193 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__); in bcm2835_aux_write()
197 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__); in bcm2835_aux_write()
201 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__); in bcm2835_aux_write()
[all …]
H A Dibex_uart.c207 qemu_log_mask(LOG_GUEST_ERROR, "ibex_uart: TX FIFO overflow"); in uart_write_tx_fifo()
279 qemu_log_mask(LOG_GUEST_ERROR, in ibex_uart_read()
304 qemu_log_mask(LOG_GUEST_ERROR, in ibex_uart_read()
317 qemu_log_mask(LOG_UNIMP, in ibex_uart_read()
323 qemu_log_mask(LOG_UNIMP, in ibex_uart_read()
328 qemu_log_mask(LOG_UNIMP, in ibex_uart_read()
333 qemu_log_mask(LOG_UNIMP, in ibex_uart_read()
337 qemu_log_mask(LOG_GUEST_ERROR, in ibex_uart_read()
370 qemu_log_mask(LOG_UNIMP, in ibex_uart_write()
374 qemu_log_mask(LOG_UNIMP, in ibex_uart_write()
[all …]
/openbmc/qemu/hw/misc/
H A Diotkit-sysctl.c352 qemu_log_mask(LOG_GUEST_ERROR, in iotkit_sysctl_read()
359 qemu_log_mask(LOG_GUEST_ERROR, in iotkit_sysctl_read()
402 qemu_log_mask(LOG_UNIMP, in iotkit_sysctl_write()
407 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl RESET_MASK unimplemented\n"); in iotkit_sysctl_write()
423 qemu_log_mask(LOG_GUEST_ERROR, in iotkit_sysctl_write()
456 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl WICCTRL unimplemented\n"); in iotkit_sysctl_write()
469 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SECDBGSET unimplemented\n"); in iotkit_sysctl_write()
488 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n"); in iotkit_sysctl_write()
501 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n"); in iotkit_sysctl_write()
514 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n"); in iotkit_sysctl_write()
[all …]
H A Dstm32l4x5_syscfg.c131 qemu_log_mask(LOG_GUEST_ERROR, in stm32l4x5_syscfg_read()
145 qemu_log_mask(LOG_UNIMP, in stm32l4x5_syscfg_write()
151 qemu_log_mask(LOG_UNIMP, in stm32l4x5_syscfg_write()
163 qemu_log_mask(LOG_UNIMP, in stm32l4x5_syscfg_write()
174 qemu_log_mask(LOG_UNIMP, in stm32l4x5_syscfg_write()
183 qemu_log_mask(LOG_UNIMP, in stm32l4x5_syscfg_write()
190 qemu_log_mask(LOG_UNIMP, in stm32l4x5_syscfg_write()
196 qemu_log_mask(LOG_UNIMP, in stm32l4x5_syscfg_write()
203 qemu_log_mask(LOG_GUEST_ERROR, in stm32l4x5_syscfg_write()
H A Daspeed_hace.c176 qemu_log_mask(LOG_GUEST_ERROR, "qcrypto hash failed : %s", in do_hash_operation()
191 qemu_log_mask(LOG_GUEST_ERROR, in do_hash_operation()
209 qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); in do_hash_operation()
234 qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); in do_hash_operation()
257 qemu_log_mask(LOG_GUEST_ERROR, "qcrypto hash update failed : %s", in do_hash_operation()
266 qemu_log_mask(LOG_GUEST_ERROR, in do_hash_operation()
281 qemu_log_mask(LOG_GUEST_ERROR, "qcrypto hash bytesv failed : %s", in do_hash_operation()
290 qemu_log_mask(LOG_GUEST_ERROR, in do_hash_operation()
314 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_hace_read()
332 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_hace_write()
[all …]
H A Darm_integrator_debug.c39 qemu_log_mask(LOG_UNIMP, in intdbg_control_read()
44 qemu_log_mask(LOG_GUEST_ERROR, in intdbg_control_read()
59 qemu_log_mask(LOG_UNIMP, in intdbg_control_write()
65 qemu_log_mask(LOG_GUEST_ERROR, in intdbg_control_write()
/openbmc/qemu/hw/ppc/
H A Dpnv_chiptod.c149 qemu_log_mask(LOG_UNIMP, "pnv_chiptod: unimplemented register: Ox%" in pnv_chiptod_xscom_read()
163 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: received TTYPE4 in " in chiptod_receive_ttype()
175 qemu_log_mask(LOG_UNIMP, "pnv_chiptod: received unimplemented " in chiptod_receive_ttype()
242 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: SCOM addressing: " in chiptod_power9_tx_ttype_target()
267 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: SCOM addressing: " in chiptod_power10_tx_ttype_target()
280 qemu_log_mask(LOG_UNIMP, "pnv_chiptod: TX TTYPE Core ID " in chiptod_power10_tx_ttype_target()
318 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" in pnv_chiptod_xscom_write()
328 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" in pnv_chiptod_xscom_write()
337 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: LOAD_TOG_REG in " in pnv_chiptod_xscom_write()
356 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" in pnv_chiptod_xscom_write()
[all …]
H A Dpnv_adu.c51 qemu_log_mask(LOG_UNIMP, "ADU: LPC_BASE_REG is not implemented\n"); in pnv_adu_xscom_read()
64 qemu_log_mask(LOG_UNIMP, "ADU Unimplemented read register: Ox%08x\n", in pnv_adu_xscom_read()
108 qemu_log_mask(LOG_UNIMP, in pnv_adu_xscom_write()
120 qemu_log_mask(LOG_GUEST_ERROR, "ADU: Unsupported LPC access " in pnv_adu_xscom_write()
145 qemu_log_mask(LOG_GUEST_ERROR, "ADU: Unsupported LPC access " in pnv_adu_xscom_write()
156 qemu_log_mask(LOG_UNIMP, in pnv_adu_xscom_write()
161 qemu_log_mask(LOG_UNIMP, "ADU Unimplemented write register: Ox%08x\n", in pnv_adu_xscom_write()
H A Dpnv_i2c.c32 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid bus number %d/%d\n", port, in pnv_i2c_get_bus()
52 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); in pnv_i2c_update_irq()
134 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); in pnv_i2c_fifo_flush()
175 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid command 0x%"PRIx64"\n", in pnv_i2c_handle_cmd()
182 qemu_log_mask(LOG_GUEST_ERROR, "I2C: command in progress\n"); in pnv_i2c_handle_cmd()
187 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); in pnv_i2c_handle_cmd()
226 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); in pnv_i2c_fifo_in()
232 qemu_log_mask(LOG_GUEST_ERROR, "I2C: no command in progress\n"); in pnv_i2c_fifo_in()
238 qemu_log_mask(LOG_GUEST_ERROR, "I2C: read command in progress\n"); in pnv_i2c_fifo_in()
261 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); in pnv_i2c_fifo_out()
[all …]
/openbmc/qemu/hw/adc/
H A Dstm32f2xx_adc.c108 qemu_log_mask(LOG_UNIMP, in stm32f2xx_adc_read()
127 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_adc_read()
142 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_adc_read()
150 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_adc_read()
163 qemu_log_mask(LOG_GUEST_ERROR, in stm32f2xx_adc_read()
180 qemu_log_mask(LOG_UNIMP, in stm32f2xx_adc_write()
205 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_adc_write()
226 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_adc_write()
235 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_adc_write()
240 qemu_log_mask(LOG_GUEST_ERROR, in stm32f2xx_adc_write()
/openbmc/qemu/target/arm/tcg/
H A Dm_helper.c229 qemu_log_mask(CPU_LOG_INT, in v7m_stack_write()
234 qemu_log_mask(CPU_LOG_INT, in v7m_stack_write()
245 qemu_log_mask(CPU_LOG_INT, in v7m_stack_write()
249 qemu_log_mask(CPU_LOG_INT, in v7m_stack_write()
263 qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.LSPERR\n"); in v7m_stack_write()
266 qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.STKERR\n"); in v7m_stack_write()
317 qemu_log_mask(CPU_LOG_INT, in v7m_stack_read()
324 qemu_log_mask(CPU_LOG_INT, in v7m_stack_read()
337 qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n"); in v7m_stack_read()
622 qemu_log_mask(LOG_GUEST_ERROR, in HELPER()
[all …]
/openbmc/qemu/hw/timer/
H A Dsh_timer.c79 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", in sh_timer_read()
136 qemu_log_mask(LOG_GUEST_ERROR, in sh_timer_write()
150 qemu_log_mask(LOG_GUEST_ERROR, in sh_timer_write()
163 qemu_log_mask(LOG_GUEST_ERROR, in sh_timer_write()
173 qemu_log_mask(LOG_GUEST_ERROR, in sh_timer_write()
180 qemu_log_mask(LOG_GUEST_ERROR, in sh_timer_write()
199 qemu_log_mask(LOG_GUEST_ERROR, in sh_timer_write()
270 qemu_log_mask(LOG_GUEST_ERROR, in tmu012_read()
290 qemu_log_mask(LOG_GUEST_ERROR, in tmu012_read()
303 qemu_log_mask(LOG_GUEST_ERROR, in tmu012_write()
[all …]
H A Dibex_timer.c144 qemu_log_mask(LOG_GUEST_ERROR, in ibex_timer_read()
172 qemu_log_mask(LOG_GUEST_ERROR, in ibex_timer_read()
176 qemu_log_mask(LOG_GUEST_ERROR, in ibex_timer_read()
192 qemu_log_mask(LOG_UNIMP, "Alert triggering not supported"); in ibex_timer_write()
198 qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported"); in ibex_timer_write()
202 qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported"); in ibex_timer_write()
205 qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported"); in ibex_timer_write()
229 qemu_log_mask(LOG_GUEST_ERROR, in ibex_timer_write()
/openbmc/qemu/hw/virtio/
H A Dvirtio-mmio.c143 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_read()
180 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_read()
190 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_read()
203 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_read()
233 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_read()
238 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_read()
298 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_write()
314 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_write()
334 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_write()
364 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_write()
[all …]
/openbmc/qemu/hw/net/
H A Dftgmac100.c363 qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", in do_phy_read()
368 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", in do_phy_read()
409 qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", in do_phy_write()
413 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", in do_phy_write()
425 qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__); in do_phy_new_ctl()
445 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n", in do_phy_new_ctl()
463 qemu_log_mask(LOG_GUEST_ERROR, "%s: no OP code %08x\n", in do_phy_ctl()
472 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read descriptor @ 0x%" in ftgmac100_read_bd()
493 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to write descriptor @ 0x%" in ftgmac100_write_bd()
507 qemu_log_mask(LOG_GUEST_ERROR, in ftgmac100_insert_vlan()
[all …]
/openbmc/qemu/target/arm/
H A Darm-powerctl.c46 qemu_log_mask(LOG_GUEST_ERROR, in arm_get_cpu_by_id()
129 qemu_log_mask(LOG_GUEST_ERROR, in arm_set_cpu_on()
153 qemu_log_mask(LOG_UNIMP, in arm_set_cpu_on()
167 qemu_log_mask(LOG_GUEST_ERROR, in arm_set_cpu_on()
220 qemu_log_mask(LOG_GUEST_ERROR, in arm_set_cpu_on_and_reset()
233 qemu_log_mask(LOG_GUEST_ERROR, in arm_set_cpu_on_and_reset()
273 qemu_log_mask(LOG_GUEST_ERROR, in arm_set_cpu_off()
310 qemu_log_mask(LOG_GUEST_ERROR, in arm_reset_cpu()
/openbmc/qemu/hw/intc/
H A Darm_gicv3_its.c367 qemu_log_mask(LOG_GUEST_ERROR, in lookup_ite()
377 qemu_log_mask(LOG_GUEST_ERROR, in lookup_ite()
385 qemu_log_mask(LOG_GUEST_ERROR, in lookup_ite()
396 qemu_log_mask(LOG_GUEST_ERROR, in lookup_ite()
417 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid ICID 0x%x\n", who, icid); in lookup_cte()
424 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid CTE\n", who); in lookup_cte()
446 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid VPEID 0x%x\n", who, vpeid); in lookup_vte()
454 qemu_log_mask(LOG_GUEST_ERROR, in lookup_vte()
492 qemu_log_mask(LOG_GUEST_ERROR, "%s: intid 0x%x out of range\n", in process_its_cmd_virt()
536 qemu_log_mask(LOG_GUEST_ERROR, in do_process_its_cmd()
[all …]
H A Daspeed_vic.c66 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", in aspeed_vic_set_irq()
166 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_vic_read()
172 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_vic_read()
236 qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. " in aspeed_vic_write()
241 qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. " in aspeed_vic_write()
252 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_vic_write()
271 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_vic_write()
277 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_vic_write()
/openbmc/qemu/target/ppc/
H A Dmmu-booke.c39 qemu_log_mask(CPU_LOG_MMU, "%s: TLB %d address " TARGET_FMT_lx in ppcemb_tlb_check()
88 qemu_log_mask(CPU_LOG_MMU, in mmu40x_get_physical_address()
126 qemu_log_mask(CPU_LOG_MMU, "%s: access %s " TARGET_FMT_lx " => " in mmu40x_get_physical_address()
162 qemu_log_mask(CPU_LOG_MMU, "%s: TLB entry not found\n", __func__); in mmubooke_check_tlb()
170 qemu_log_mask(CPU_LOG_MMU, "%s: AS doesn't match\n", __func__); in mmubooke_check_tlb()
180 qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__); in mmubooke_check_tlb()
184 qemu_log_mask(CPU_LOG_MMU, "%s: no prot match: %x\n", __func__, *prot); in mmubooke_check_tlb()
203 qemu_log_mask(CPU_LOG_MMU, in mmubooke_get_physical_address()
237 qemu_log_mask(CPU_LOG_MMU, "%s: TLB ADDR=0x" TARGET_FMT_lx in ppcmas_tlb_check()
341 qemu_log_mask(CPU_LOG_MMU, "%s: No TLB entry found for effective address " in mmubooke206_check_tlb()
[all …]
H A Dmmu_common.c43 qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value); in ppc_store_sdr1()
51 qemu_log_mask(LOG_GUEST_ERROR, "Invalid bits 0x"TARGET_FMT_lx in ppc_store_sdr1()
56 qemu_log_mask(LOG_GUEST_ERROR, "Invalid HTABSIZE 0x" TARGET_FMT_lx in ppc_store_sdr1()
106 qemu_log_mask(CPU_LOG_MMU, "TLB %d/%d %s [" TARGET_FMT_lx in ppc6xx_tlb_check()
113 qemu_log_mask(CPU_LOG_MMU, "TLB %d/%d %s " TARGET_FMT_lx " <> " in ppc6xx_tlb_check()
128 qemu_log_mask(CPU_LOG_MMU, "Bad RPN/WIMG/PP\n"); in ppc6xx_tlb_check()
137 qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); in ppc6xx_tlb_check()
141 qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); in ppc6xx_tlb_check()
146 qemu_log_mask(CPU_LOG_MMU, "found TLB at addr " HWADDR_FMT_plx in ppc6xx_tlb_check()
199 qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT v " TARGET_FMT_lx "\n", __func__, in get_bat_6xx_tlb()
[all …]
/openbmc/qemu/hw/gpio/
H A Dstm32l4x5_gpio.c103 qemu_log_mask(LOG_GUEST_ERROR, "Line %d can't be driven externally\n", in stm32l4x5_gpio_set()
212 qemu_log_mask(LOG_GUEST_ERROR, in get_gpio_pinmask_to_disconnect()
269 qemu_log_mask(LOG_UNIMP, in stm32l4x5_gpio_write()
279 qemu_log_mask(LOG_UNIMP, in stm32l4x5_gpio_write()
290 qemu_log_mask(LOG_UNIMP, in stm32l4x5_gpio_write()
308 qemu_log_mask(LOG_UNIMP, in stm32l4x5_gpio_write()
314 qemu_log_mask(LOG_UNIMP, in stm32l4x5_gpio_write()
320 qemu_log_mask(LOG_UNIMP, in stm32l4x5_gpio_write()
332 qemu_log_mask(LOG_UNIMP, in stm32l4x5_gpio_write()
338 qemu_log_mask(LOG_GUEST_ERROR, in stm32l4x5_gpio_write()
[all …]

12345678910>>...21