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Searched refs:qdev_prop_set_uint32 (Results 1 – 25 of 112) sorted by relevance

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/openbmc/qemu/hw/riscv/
H A Dmicroblaze-v-generic.c83 qdev_prop_set_uint32(dev, "kind-of-intr", in mb_v_generic_init()
109 qdev_prop_set_uint32(dev, "one-timer-only", 0); in mb_v_generic_init()
110 qdev_prop_set_uint32(dev, "clock-frequency", 100000000); in mb_v_generic_init()
118 qdev_prop_set_uint32(dev, "one-timer-only", 0); in mb_v_generic_init()
119 qdev_prop_set_uint32(dev, "clock-frequency", 100000000); in mb_v_generic_init()
128 qdev_prop_set_uint32(dev, "tx-ping-pong", 0); in mb_v_generic_init()
129 qdev_prop_set_uint32(dev, "rx-ping-pong", 0); in mb_v_generic_init()
147 qdev_prop_set_uint32(eth0, "rxmem", 0x1000); in mb_v_generic_init()
148 qdev_prop_set_uint32(eth0, "txmem", 0x1000); in mb_v_generic_init()
161 qdev_prop_set_uint32(dma, "freqhz", 100000000); in mb_v_generic_init()
H A Dopentitan.c182 qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180); in lowrisc_ibex_soc_realize()
183 qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3); in lowrisc_ibex_soc_realize()
184 qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000); in lowrisc_ibex_soc_realize()
185 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000); in lowrisc_ibex_soc_realize()
186 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32); in lowrisc_ibex_soc_realize()
187 qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000); in lowrisc_ibex_soc_realize()
188 qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8); in lowrisc_ibex_soc_realize()
189 qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size); in lowrisc_ibex_soc_realize()
/openbmc/qemu/hw/isa/
H A Disa-superio.c59 qdev_prop_set_uint32(d, "index", i); in isa_superio_realize()
61 qdev_prop_set_uint32(d, "iobase", in isa_superio_realize()
65 qdev_prop_set_uint32(d, "irq", k->parallel.get_irq(sio, i)); in isa_superio_realize()
98 qdev_prop_set_uint32(d, "index", i); in isa_superio_realize()
100 qdev_prop_set_uint32(d, "iobase", in isa_superio_realize()
104 qdev_prop_set_uint32(d, "irq", k->serial.get_irq(sio, i)); in isa_superio_realize()
126 qdev_prop_set_uint32(d, "iobase", k->floppy.get_iobase(sio, 0)); in isa_superio_realize()
129 qdev_prop_set_uint32(d, "irq", k->floppy.get_irq(sio, 0)); in isa_superio_realize()
157 qdev_prop_set_uint32(d, "iobase", k->ide.get_iobase(sio, 0)); in isa_superio_realize()
160 qdev_prop_set_uint32( in isa_superio_realize()
[all...]
/openbmc/qemu/hw/cpu/
H A Darm11mpcore.c80 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); in mpcore_priv_realize()
85 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); in mpcore_priv_realize()
86 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); in mpcore_priv_realize()
87 qdev_prop_set_uint32(gicdev, "num-priority-bits", in mpcore_priv_realize()
101 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); in mpcore_priv_realize()
106 qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu); in mpcore_priv_realize()
127 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0); in mpcore_priv_initfn()
H A Da9mpcore.c74 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); in a9mp_priv_realize()
81 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); in a9mp_priv_realize()
82 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); in a9mp_priv_realize()
83 qdev_prop_set_uint32(gicdev, "num-priority-bits", in a9mp_priv_realize()
105 qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); in a9mp_priv_realize()
112 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); in a9mp_priv_realize()
119 qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); in a9mp_priv_realize()
H A Da15mpcore.c47 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); in a15mp_priv_initfn()
67 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); in a15mp_priv_realize()
68 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); in a15mp_priv_realize()
/openbmc/qemu/hw/microblaze/
H A Dpetalogix_ml605_mmu.c115 qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ); in petalogix_ml605_init()
131 qdev_prop_set_uint32(dev, "one-timer-only", 0); in petalogix_ml605_init()
132 qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000); in petalogix_ml605_init()
150 qdev_prop_set_uint32(eth0, "rxmem", 0x1000); in petalogix_ml605_init()
151 qdev_prop_set_uint32(eth0, "txmem", 0x1000); in petalogix_ml605_init()
164 qdev_prop_set_uint32(dma, "freqhz", 100 * 1000000); in petalogix_ml605_init()
H A Dpetalogix_s3adsp1800_mmu.c111 qdev_prop_set_uint32(dev, "kind-of-intr", in OBJECT_DECLARE_TYPE()
131 qdev_prop_set_uint32(dev, "one-timer-only", 0); in OBJECT_DECLARE_TYPE()
132 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); in OBJECT_DECLARE_TYPE()
140 qdev_prop_set_uint32(dev, "tx-ping-pong", 0); in OBJECT_DECLARE_TYPE()
141 qdev_prop_set_uint32(dev, "rx-ping-pong", 0); in OBJECT_DECLARE_TYPE()
/openbmc/qemu/include/hw/net/
H A Dne2000-isa.h29 qdev_prop_set_uint32(dev, "iobase", base); in isa_ne2000_init()
30 qdev_prop_set_uint32(dev, "irq", irq); in isa_ne2000_init()
/openbmc/qemu/hw/misc/macio/
H A Dmacio.c105 qdev_prop_set_uint32(DEVICE(&s->escc), "disabled", 0); in macio_common_realize()
106 qdev_prop_set_uint32(DEVICE(&s->escc), "frequency", ESCC_CLOCK); in macio_common_realize()
107 qdev_prop_set_uint32(DEVICE(&s->escc), "it_shift", 4); in macio_common_realize()
108 qdev_prop_set_uint32(DEVICE(&s->escc), "chnBtype", escc_serial); in macio_common_realize()
109 qdev_prop_set_uint32(DEVICE(&s->escc), "chnAtype", escc_serial); in macio_common_realize()
126 qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid); in macio_realize_ide()
202 qdev_prop_set_uint32(DEVICE(ide), "addr", addr); in macio_init_ide()
220 qdev_prop_set_uint32(dev, "size", MACIO_NVRAM_SIZE); in macio_oldworld_init()
221 qdev_prop_set_uint32(dev, "it_shift", 4); in macio_oldworld_init()
275 qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO); in macio_newworld_realize()
/openbmc/qemu/hw/ide/
H A Disa.c89 qdev_prop_set_uint32(dev, "iobase", iobase); in isa_ide_init()
90 qdev_prop_set_uint32(dev, "iobase2", iobase2); in isa_ide_init()
91 qdev_prop_set_uint32(dev, "irq", irqnum); in isa_ide_init()
/openbmc/qemu/hw/arm/
H A Dmps2.c228 qdev_prop_set_uint32(armv7m, "num-irq", 32); in mps2_common_init()
232 qdev_prop_set_uint32(armv7m, "mpu-ns-regions", 16); in mps2_common_init()
233 qdev_prop_set_uint32(armv7m, "num-irq", 32); in mps2_common_init()
236 qdev_prop_set_uint32(armv7m, "num-irq", 64); in mps2_common_init()
305 qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ); in mps2_common_init()
349 qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ); in mps2_common_init()
402 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); in mps2_common_init()
403 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); in mps2_common_init()
404 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); in mps2_common_init()
416 qdev_prop_set_uint32(DEVIC in mps2_common_init()
[all...]
H A Dmps3r.c271 qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus); in create_gic()
272 qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL); in create_gic()
342 qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ); in create_uart()
422 qdev_prop_set_uint32(orgate, "num-lines", 2); in mps3r_common_init()
440 qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines", in mps3r_common_init()
517 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0); in mps3r_common_init()
518 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2); in mps3r_common_init()
519 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008); in mps3r_common_init()
520 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360); in mps3r_common_init()
533 qdev_prop_set_uint32(DEVIC in mps3r_common_init()
[all...]
H A Dmsf2-soc.c136 qdev_prop_set_uint32(armv7m, "num-irq", 81); in m2sxxx_soc_realize()
161 qdev_prop_set_uint32(dev, "clock-frequency", in m2sxxx_soc_realize()
174 qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div); in m2sxxx_soc_realize()
175 qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div); in m2sxxx_soc_realize()
H A Drealview.c67 qdev_prop_set_uint32(splitter, "num-lines", 2); in split_irq_from_named()
185 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); in realview_init()
186 qdev_prop_set_uint32(sysctl, "proc_id", proc_id); in realview_init()
193 qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); in realview_init()
197 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); in realview_init()
217 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); in realview_init()
H A Dmsf2-som.c77 qdev_prop_set_uint32(dev, "apb0div", 2); in emcraft_sf2_s2s010_init()
78 qdev_prop_set_uint32(dev, "apb1div", 2); in emcraft_sf2_s2s010_init()
/openbmc/qemu/hw/intc/
H A Dsifive_plic.c491 qdev_prop_set_uint32(dev, "hartid-base", hartid_base); in type_init()
492 qdev_prop_set_uint32(dev, "num-sources", num_sources); in type_init()
493 qdev_prop_set_uint32(dev, "num-priorities", num_priorities); in type_init()
494 qdev_prop_set_uint32(dev, "priority-base", priority_base); in type_init()
495 qdev_prop_set_uint32(dev, "pending-base", pending_base); in type_init()
496 qdev_prop_set_uint32(dev, "enable-base", enable_base); in type_init()
497 qdev_prop_set_uint32(dev, "enable-stride", enable_stride); in type_init()
498 qdev_prop_set_uint32(dev, "context-base", context_base); in type_init()
499 qdev_prop_set_uint32(dev, "context-stride", context_stride); in type_init()
500 qdev_prop_set_uint32(dev, "aperture-size", aperture_size); in type_init()
H A Driscv_aclint.c378 qdev_prop_set_uint32(dev, "hartid-base", hartid_base); in riscv_aclint_mtimer_create()
379 qdev_prop_set_uint32(dev, "num-harts", num_harts); in riscv_aclint_mtimer_create()
380 qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base); in riscv_aclint_mtimer_create()
381 qdev_prop_set_uint32(dev, "time-base", time_base); in riscv_aclint_mtimer_create()
382 qdev_prop_set_uint32(dev, "aperture-size", size); in riscv_aclint_mtimer_create()
383 qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq); in riscv_aclint_mtimer_create()
558 qdev_prop_set_uint32(dev, "hartid-base", hartid_base); in riscv_aclint_swi_create()
559 qdev_prop_set_uint32(dev, "num-harts", num_harts); in riscv_aclint_swi_create()
560 qdev_prop_set_uint32(dev, "sswi", sswi ? true : false); in riscv_aclint_swi_create()
H A Drealview_gic.c35 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", numirq); in realview_gic_realize()
63 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", 1); in realview_gic_init()
H A Dexynos4210_gic.c64 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); in exynos4210_gic_realize()
65 qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); in exynos4210_gic_realize()
/openbmc/qemu/include/hw/timer/
H A Di8254.h56 qdev_prop_set_uint32(dev, "iobase", base); in OBJECT_DECLARE_TYPE()
72 qdev_prop_set_uint32(dev, "iobase", base); in kvm_pit_init()
/openbmc/qemu/hw/ppc/
H A Dprep.c315 qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc); in ibm_40p_init()
316 qdev_prop_set_uint32(dev, "equipment", 0xc0); in ibm_40p_init()
322 qdev_prop_set_uint32(dev, "ram-size", machine->ram_size); in ibm_40p_init()
342 qdev_prop_set_uint32(dev, "iobase", 0x830); in ibm_40p_init()
343 qdev_prop_set_uint32(dev, "irq", 10); in ibm_40p_init()
351 qdev_prop_set_uint32(dev, "config", 12); in ibm_40p_init()
369 qdev_prop_set_uint32(dev, "data_width", 1); in ibm_40p_init()
/openbmc/qemu/hw/sparc/
H A Dsun4m.c288 qdev_prop_set_uint32(dev, "version", version); in iommu_init()
382 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); in slavio_timer_init_all()
457 qdev_prop_set_uint32(dev, "version", version); in ecc_init()
487 qdev_prop_set_uint32(dev, "vram_size", vram_size); in tcx_init()
539 qdev_prop_set_uint32(dev, "vram-size", vram_size); in cg3_init()
962 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); in sun4m_hw_init()
963 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); in sun4m_hw_init()
964 qdev_prop_set_uint32(dev, "it_shift", 1); in sun4m_hw_init()
967 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); in sun4m_hw_init()
968 qdev_prop_set_uint32(de in sun4m_hw_init()
[all...]
/openbmc/qemu/hw/m68k/
H A Dq800.c429 qdev_prop_set_uint32(dev, "disabled", 0); in q800_machine_init()
430 qdev_prop_set_uint32(dev, "frequency", MAC_CLOCK); in q800_machine_init()
431 qdev_prop_set_uint32(dev, "it_shift", 1); in q800_machine_init()
435 qdev_prop_set_uint32(dev, "chnBtype", 0); in q800_machine_init()
436 qdev_prop_set_uint32(dev, "chnAtype", 0); in q800_machine_init()
527 qdev_prop_set_uint32(DEVICE(&m->mac_nubus_bridge), "slot-available-mask", in q800_machine_init()
562 qdev_prop_set_uint32(dev, "slot", 9); in q800_machine_init()
563 qdev_prop_set_uint32(dev, "width", graphic_width); in q800_machine_init()
564 qdev_prop_set_uint32(dev, "height", graphic_height); in q800_machine_init()
/openbmc/qemu/hw/vmapple/
H A Dvmapple.c194 qdev_prop_set_uint32(vms->cfg, "nr-cpus", machine->smp.cpus); in create_cfg()
197 qdev_prop_set_uint32(vms->cfg, "rnd", rnd); in create_cfg()
248 qdev_prop_set_uint32(vms->gic, "revision", 3); in create_gic()
249 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); in create_gic()
254 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); in create_gic()
389 qdev_prop_set_uint32(dev, "num-irqs", GPEX_NUM_IRQS); in create_pcie()

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