Searched refs:psc0 (Results 1 – 9 of 9) sorted by relevance
53 mdstat = &psc_regs->psc0.mdstat[id]; in lpsc_transition()54 mdctl = &psc_regs->psc0.mdctl[id]; in lpsc_transition()
64 clocks = <&psc0 15>;65 resets = <&psc0 15>;76 psc0: clock-controller@10000 { label77 compatible = "ti,da850-psc0";383 power-domains = <&psc0 0>;390 power-domains = <&psc0 1>;397 power-domains = <&psc0 2>;424 clocks = <&psc0 9>;425 power-domains = <&psc0 9>;497 clocks = <&psc0 5>;[all …]
319 psc0 = <0x97>;
49 mdstat = &psc_regs->psc0.mdstat[id]; in dsp_lpsc_on()50 mdctl = &psc_regs->psc0.mdctl[id]; in dsp_lpsc_on()
266 mdstat = &psc_regs->psc0.mdstat[id]; in dsp_lpsc_on()267 mdctl = &psc_regs->psc0.mdctl[id]; in dsp_lpsc_on()
108 mdstat = &psc_regs->psc0.mdstat[id]; in dsp_lpsc_on()109 mdctl = &psc_regs->psc0.mdctl[id]; in dsp_lpsc_on()
455 MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE); in __mvgbe_init()466 MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE in __mvgbe_init()467 | (MVGBE_REG_RD(regs->psc0) & MRU_MASK)); in __mvgbe_init()470 MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN); in __mvgbe_init()527 MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN); in __mvgbe_halt()
378 u32 psc0; member
345 } psc0; member