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Searched refs:pp_smu (Results 1 – 25 of 36) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_pp_smu.h48 struct pp_smu { struct
97 struct pp_smu pp_smu; member
103 void (*set_display_count)(struct pp_smu *pp, int count);
112 void (*set_wm_ranges)(struct pp_smu *pp,
118 void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz);
124 void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz);
129 void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz);
134 void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz);
137 void (*set_pme_wa_enable)(struct pp_smu *pp);
168 struct pp_smu pp_smu; member
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr.c198 struct pp_smu_funcs_rv *pp_smu = NULL; in rv1_update_clocks() local
205 ASSERT(clk_mgr->pp_smu); in rv1_update_clocks()
210 pp_smu = &clk_mgr->pp_smu->rv_funcs; in rv1_update_clocks()
223 if (pp_smu->set_display_count) in rv1_update_clocks()
224 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in rv1_update_clocks()
264 if (pp_smu->set_hard_min_fclk_by_freq && in rv1_update_clocks()
265 pp_smu->set_hard_min_dcfclk_by_freq && in rv1_update_clocks()
266 pp_smu->set_min_deep_sleep_dcfclk) { in rv1_update_clocks()
267 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
268 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
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H A Drv2_clk_mgr.c37 …gr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu) in rv2_clk_mgr_construct() argument
40 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in rv2_clk_mgr_construct()
H A Drv2_clk_mgr.h29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
H A Drv1_clk_mgr.h29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c223 struct pp_smu_funcs_nv *pp_smu = NULL; in dcn2_update_clocks() local
247 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
248 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
254 if (pp_smu && pp_smu->set_display_count) in dcn2_update_clocks()
255 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in dcn2_update_clocks()
264 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) in dcn2_update_clocks()
265 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks()
271 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) in dcn2_update_clocks()
272 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_… in dcn2_update_clocks()
277 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq) in dcn2_update_clocks()
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H A Ddcn20_clk_mgr.h43 struct pp_smu_funcs *pp_smu,
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/
H A Dclk_mgr.c151 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg … in dc_clk_mgr_create() argument
237 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
242 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
246 rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu); in dc_clk_mgr_create()
251 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in dc_clk_mgr_create()
264 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
268 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
272 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
276 dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
279 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c464 static void pp_rv_set_wm_ranges(struct pp_smu *pp, in pp_rv_set_wm_ranges()
513 static void pp_rv_set_pme_wa_enable(struct pp_smu *pp) in pp_rv_set_pme_wa_enable()
521 static void pp_rv_set_active_display_count(struct pp_smu *pp, int count) in pp_rv_set_active_display_count()
529 static void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock) in pp_rv_set_min_deep_sleep_dcfclk()
537 static void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock) in pp_rv_set_hard_min_dcefclk_by_freq()
545 static void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz) in pp_rv_set_hard_min_fclk_by_freq()
553 static enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp, in pp_nv_set_wm_ranges()
564 static enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count) in pp_nv_set_display_count()
581 pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz) in pp_nv_set_min_deep_sleep_dcfclk()
598 struct pp_smu *pp, int mhz) in pp_nv_set_hard_min_dcefclk_by_freq()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c516 struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu; in rn_notify_wm_ranges() local
522 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges) in rn_notify_wm_ranges()
523 pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges); in rn_notify_wm_ranges()
702 struct pp_smu_funcs *pp_smu, in rn_clk_mgr_construct() argument
718 clk_mgr->pp_smu = pp_smu; in rn_clk_mgr_construct()
772 if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) { in rn_clk_mgr_construct()
773 status = pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table); in rn_clk_mgr_construct()
H A Drn_clk_mgr.h46 struct pp_smu_funcs *pp_smu,
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_resource.c481 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
789 if (pool->base.pp_smu != NULL) in dcn21_resource_destruct()
790 dcn21_pp_smu_destroy(&pool->base.pp_smu); in dcn21_resource_destruct()
1125 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); in dcn21_pp_smu_create() local
1127 if (!pp_smu) in dcn21_pp_smu_create()
1128 return pp_smu; in dcn21_pp_smu_create()
1130 dm_pp_get_funcs(ctx, pp_smu); in dcn21_pp_smu_create()
1132 if (pp_smu->ctx.ver != PP_SMU_VER_RN) in dcn21_pp_smu_create()
1133 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); in dcn21_pp_smu_create()
1136 return pp_smu; in dcn21_pp_smu_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c1054 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1189 if (pool->base.pp_smu != NULL) in dcn20_resource_destruct()
1190 dcn20_pp_smu_destroy(&pool->base.pp_smu); in dcn20_resource_destruct()
2283 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC); in dcn20_pp_smu_create() local
2285 if (!pp_smu) in dcn20_pp_smu_create()
2286 return pp_smu; in dcn20_pp_smu_create()
2288 dm_pp_get_funcs(ctx, pp_smu); in dcn20_pp_smu_create()
2290 if (pp_smu->ctx.ver != PP_SMU_VER_NV) in dcn20_pp_smu_create()
2291 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); in dcn20_pp_smu_create()
2293 return pp_smu; in dcn20_pp_smu_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.h31 struct pp_smu_funcs *pp_smu,
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_resource.c898 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); in dcn10_pp_smu_create() local
900 if (!pp_smu) in dcn10_pp_smu_create()
901 return pp_smu; in dcn10_pp_smu_create()
903 dm_pp_get_funcs(ctx, pp_smu); in dcn10_pp_smu_create()
904 return pp_smu; in dcn10_pp_smu_create()
983 kfree(pool->base.pp_smu); in dcn10_resource_destruct()
1487 pool->base.pp_smu = dcn10_pp_smu_create(ctx); in dcn10_resource_construct()
1493 if (pool->base.pp_smu != NULL in dcn10_resource_construct()
1494 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) in dcn10_resource_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.h32 struct pp_smu_funcs *pp_smu,
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.h44 struct pp_smu_funcs *pp_smu,
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.h44 struct pp_smu_funcs *pp_smu,
H A Ddcn316_clk_mgr.c575 struct pp_smu_funcs *pp_smu, in dcn316_clk_mgr_construct() argument
584 clk_mgr->base.pp_smu = pp_smu; in dcn316_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.h47 struct pp_smu_funcs *pp_smu,
H A Dvg_clk_mgr.c661 struct pp_smu_funcs *pp_smu, in vg_clk_mgr_construct() argument
670 clk_mgr->base.pp_smu = pp_smu; in vg_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.h52 struct pp_smu_funcs *pp_smu,
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.h51 struct pp_smu_funcs *pp_smu,
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.h93 struct pp_smu_funcs *pp_smu,
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_resource.c1320 struct pp_smu_funcs *pp_smu, in set_wm_ranges() argument
1360 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges); in set_wm_ranges()
1545 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges) in dcn301_resource_construct()
1546 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc); in dcn301_resource_construct()

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