1d5c6909eSRoman Li /* SPDX-License-Identifier: MIT */
2d5c6909eSRoman Li /*
3d5c6909eSRoman Li  * Copyright 2022 Advanced Micro Devices, Inc.
4d5c6909eSRoman Li  *
5d5c6909eSRoman Li  * Permission is hereby granted, free of charge, to any person obtaining a
6d5c6909eSRoman Li  * copy of this software and associated documentation files (the "Software"),
7d5c6909eSRoman Li  * to deal in the Software without restriction, including without limitation
8d5c6909eSRoman Li  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9d5c6909eSRoman Li  * and/or sell copies of the Software, and to permit persons to whom the
10d5c6909eSRoman Li  * Software is furnished to do so, subject to the following conditions:
11d5c6909eSRoman Li  *
12d5c6909eSRoman Li  * The above copyright notice and this permission notice shall be included in
13d5c6909eSRoman Li  * all copies or substantial portions of the Software.
14d5c6909eSRoman Li  *
15d5c6909eSRoman Li  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16d5c6909eSRoman Li  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17d5c6909eSRoman Li  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18d5c6909eSRoman Li  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19d5c6909eSRoman Li  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20d5c6909eSRoman Li  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21d5c6909eSRoman Li  * OTHER DEALINGS IN THE SOFTWARE.
22d5c6909eSRoman Li  *
23d5c6909eSRoman Li  * Authors: AMD
24d5c6909eSRoman Li  *
25d5c6909eSRoman Li  */
26d5c6909eSRoman Li 
27d5c6909eSRoman Li #ifndef __DCN314_CLK_MGR_H__
28d5c6909eSRoman Li #define __DCN314_CLK_MGR_H__
29d5c6909eSRoman Li #include "clk_mgr_internal.h"
30d5c6909eSRoman Li 
31d5c6909eSRoman Li struct dcn314_watermarks;
32d5c6909eSRoman Li 
33d5c6909eSRoman Li struct dcn314_smu_watermark_set {
34d5c6909eSRoman Li 	struct dcn314_watermarks *wm_set;
35d5c6909eSRoman Li 	union large_integer mc_address;
36d5c6909eSRoman Li };
37d5c6909eSRoman Li 
38d5c6909eSRoman Li struct clk_mgr_dcn314 {
39d5c6909eSRoman Li 	struct clk_mgr_internal base;
40d5c6909eSRoman Li 	struct dcn314_smu_watermark_set smu_wm_set;
41d5c6909eSRoman Li };
42d5c6909eSRoman Li 
43d5c6909eSRoman Li bool dcn314_are_clock_states_equal(struct dc_clocks *a,
44d5c6909eSRoman Li 		struct dc_clocks *b);
45*20511605SDuncan Ma 
46d5c6909eSRoman Li void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,
47d5c6909eSRoman Li 			struct dc_state *context,
48d5c6909eSRoman Li 			bool safe_to_lower);
49d5c6909eSRoman Li 
50d5c6909eSRoman Li void dcn314_clk_mgr_construct(struct dc_context *ctx,
51d5c6909eSRoman Li 		struct clk_mgr_dcn314 *clk_mgr,
52d5c6909eSRoman Li 		struct pp_smu_funcs *pp_smu,
53d5c6909eSRoman Li 		struct dccg *dccg);
54d5c6909eSRoman Li 
55d5c6909eSRoman Li void dcn314_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);
56d5c6909eSRoman Li 
57d5c6909eSRoman Li #endif //__DCN314_CLK_MGR_H__
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