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Searched refs:pmu_spare1 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Ddmc_init_ddr3.c803 dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1)); in ddr3_mem_ctrl_init()
811 writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1); in ddr3_mem_ctrl_init()
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dpower.h291 unsigned int pmu_spare1; member
915 unsigned int pmu_spare1; /* Store PHY0_CON4 for read leveling */ member