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Searched refs:pmc (Results 1 – 25 of 92) sorted by relevance

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/openbmc/u-boot/arch/arm/mach-at91/
H A Dclock.c16 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in at91_periph_clk_enable() local
25 writel(id, &pmc->pcr); in at91_periph_clk_enable()
27 div_value = readl(&pmc->pcr) & AT91_PMC_PCR_DIV; in at91_periph_clk_enable()
31 writel(regval, &pmc->pcr); in at91_periph_clk_enable()
33 writel(0x01 << id, &pmc->pcer); in at91_periph_clk_enable()
39 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in at91_periph_clk_disable() local
49 writel(regval, &pmc->pcr); in at91_periph_clk_disable()
51 writel(0x01 << id, &pmc->pcdr); in at91_periph_clk_disable()
57 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in at91_system_clk_enable() local
59 writel(sys_clk, &pmc->scer); in at91_system_clk_enable()
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H A Dspl_atmel.c19 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in switch_to_main_crystal_osc() local
22 tmp = readl(&pmc->mor); in switch_to_main_crystal_osc()
28 writel(tmp, &pmc->mor); in switch_to_main_crystal_osc()
29 while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS)) in switch_to_main_crystal_osc()
34 tmp = readl(&pmc->mcfr); in switch_to_main_crystal_osc()
37 writel(tmp, &pmc->mcfr); in switch_to_main_crystal_osc()
39 while (!(readl(&pmc->mcfr) & AT91_PMC_MCFR_MAINRDY)) in switch_to_main_crystal_osc()
42 if (!(readl(&pmc->mcfr) & AT91_PMC_MCFR_MAINF_MASK)) in switch_to_main_crystal_osc()
46 tmp = readl(&pmc->mor); in switch_to_main_crystal_osc()
50 writel(tmp, &pmc->mor); in switch_to_main_crystal_osc()
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H A Dspl_at91.c32 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in lowlevel_clock_init() local
34 if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) { in lowlevel_clock_init()
36 writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor); in lowlevel_clock_init()
39 while (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) in lowlevel_clock_init()
44 if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) { in lowlevel_clock_init()
47 tmp = readl(&pmc->mckr); in lowlevel_clock_init()
50 writel(tmp, &pmc->mckr); in lowlevel_clock_init()
51 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in lowlevel_clock_init()
56 writel(tmp, &pmc->mckr); in lowlevel_clock_init()
57 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in lowlevel_clock_init()
/openbmc/qemu/hw/ppc/
H A De500plat.c35 PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); in e500plat_init() local
39 pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20; in e500plat_init()
73 PPCE500MachineClass *pmc = PPCE500_MACHINE_CLASS(oc); in e500plat_machine_class_init() local
81 pmc->pci_first_slot = 0x1; in e500plat_machine_class_init()
82 pmc->pci_nr_slots = PCI_SLOT_MAX - 1; in e500plat_machine_class_init()
83 pmc->fixup_devtree = e500plat_fixup_devtree; in e500plat_machine_class_init()
84 pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_42; in e500plat_machine_class_init()
85 pmc->has_mpc8xxx_gpio = true; in e500plat_machine_class_init()
86 pmc->has_esdhc = true; in e500plat_machine_class_init()
87 pmc->platform_bus_base = 0xf00000000ULL; in e500plat_machine_class_init()
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H A Dmpc8544ds.c43 PPCE500MachineClass *pmc = PPCE500_MACHINE_CLASS(oc); in mpc8544ds_machine_class_init() local
45 pmc->pci_first_slot = 0x11; in mpc8544ds_machine_class_init()
46 pmc->pci_nr_slots = 2; in mpc8544ds_machine_class_init()
47 pmc->fixup_devtree = mpc8544ds_fixup_devtree; in mpc8544ds_machine_class_init()
48 pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20; in mpc8544ds_machine_class_init()
49 pmc->platform_bus_base = 0xFF800000ULL; in mpc8544ds_machine_class_init()
50 pmc->platform_bus_size = 8 * MiB; in mpc8544ds_machine_class_init()
51 pmc->platform_bus_first_irq = 5; in mpc8544ds_machine_class_init()
52 pmc->platform_bus_num_irqs = 10; in mpc8544ds_machine_class_init()
53 pmc->ccsrbar_base = 0xE0000000ULL; in mpc8544ds_machine_class_init()
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H A De500.c323 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); in platform_bus_create_devtree() local
324 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); in platform_bus_create_devtree()
326 uint64_t addr = pmc->platform_bus_base; in platform_bus_create_devtree()
327 uint64_t size = pmc->platform_bus_size; in platform_bus_create_devtree()
328 int irq_start = pmc->platform_bus_first_irq; in platform_bus_create_devtree()
377 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); in ppce500_load_device_tree() local
398 0x2000000, 0x0, pmc->pci_mmio_bus_base, in ppce500_load_device_tree()
399 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, in ppce500_load_device_tree()
403 pmc in ppce500_load_device_tree()
814 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); ppce500_init_mpic_qemu() local
834 ppce500_init_mpic_kvm(const PPCE500MachineClass * pmc,Error ** errp) ppce500_init_mpic_kvm() argument
867 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); ppce500_init_mpic() local
906 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); ppce500_init() local
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/openbmc/u-boot/arch/arm/mach-at91/armv7/
H A Dclock.c58 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in at91_clock_init() local
69 tmp = readl(&pmc->mcfr); in at91_clock_init()
78 gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); in at91_clock_init()
84 mckr = readl(&pmc->mckr); in at91_clock_init()
117 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in at91_plla_init() local
119 writel(pllar, &pmc->pllar); in at91_plla_init()
120 while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) in at91_plla_init()
126 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in at91_mck_init() local
129 tmp = readl(&pmc->mckr); in at91_mck_init()
146 writel(tmp, &pmc->mckr); in at91_mck_init()
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/openbmc/u-boot/arch/arm/mach-at91/arm926ejs/
H A Dclock.c116 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; in at91_clock_init() local
127 tmp = readl(&pmc->mcfr); in at91_clock_init()
136 gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); in at91_clock_init()
155 mckr = readl(&pmc->mckr); in at91_clock_init()
204 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in at91_plla_init() local
206 writel(pllar, &pmc->pllar); in at91_plla_init()
207 while (!(readl(&pmc->sr) & AT91_PMC_LOCKA)) in at91_plla_init()
212 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in at91_pllb_init() local
214 writel(pllbr, &pmc->pllbr); in at91_pllb_init()
215 while (!(readl(&pmc->sr) & AT91_PMC_LOCKB)) in at91_pllb_init()
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/openbmc/qemu/hw/arm/
H A Dxlnx-versal.c37 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" in versal_create_apu_cpus()
1455 object_property_add_child(OBJECT(s), "pmc-iou-slcr", OBJECT(dev));
1811 slcr = DEVICE(versal_get_child(s, "pmc-iou-slcr"));
/openbmc/u-boot/arch/arm/mach-at91/arm920t/
H A Dclock.c108 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; in at91_clock_init() local
119 tmp = readl(&pmc->mcfr); in at91_clock_init()
128 gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); in at91_clock_init()
147 mckr = readl(&pmc->mckr); in at91_clock_init()
162 struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; in at91_pllb_clk_enable() local
166 writel(pllbr, &pmc->pllbr); in at91_pllb_clk_enable()
167 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) { in at91_pllb_clk_enable()
180 struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; in at91_pllb_clk_disable() local
184 writel(0, &pmc->pllbr); in at91_pllb_clk_disable()
185 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) { in at91_pllb_clk_disable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dcpu.c23 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail() local
37 writel(0x7C830, &pmc->pmc_cpupwrgood_timer); in enable_cpu_power_rail()
40 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); in enable_cpu_power_rail()
41 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); in enable_cpu_power_rail()
151 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in tegra124_init_clocks() local
168 val = readl(&pmc->pmc_osc_edpd_over); in tegra124_init_clocks()
171 writel(val, &pmc->pmc_osc_edpd_over); in tegra124_init_clocks()
174 setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN); in tegra124_init_clocks()
233 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in is_partition_powered() local
237 reg = readl(&pmc->pmc_pwrgate_status); in is_partition_powered()
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/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dcpu.c20 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail() local
35 writel(reg, &pmc->pmc_cpupwrgood_timer); in enable_cpu_power_rail()
38 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); in enable_cpu_power_rail()
39 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); in enable_cpu_power_rail()
188 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in is_partition_powered() local
192 reg = readl(&pmc->pmc_pwrgate_status); in is_partition_powered()
198 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in is_clamp_enabled() local
202 reg = readl(&pmc->pmc_clamp_status); in is_clamp_enabled()
208 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in power_partition() local
215 writel(START_CP | partid, &pmc->pmc_pwrgate_toggle); in power_partition()
/openbmc/u-boot/drivers/clk/at91/
H A Dclk-generated.c51 struct at91_pmc *pmc = plat->reg_base; in generic_clk_get_rate() local
58 writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr); in generic_clk_get_rate()
59 tmp = readl(&pmc->pcr); in generic_clk_get_rate()
79 struct at91_pmc *pmc = plat->reg_base; in generic_clk_set_rate() local
128 writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr); in generic_clk_set_rate()
129 tmp = readl(&pmc->pcr); in generic_clk_set_rate()
135 writel(tmp, &pmc->pcr); in generic_clk_set_rate()
137 while (!(readl(&pmc->sr) & AT91_PMC_GCKRDY)) in generic_clk_set_rate()
H A Dclk-plladiv.c22 struct at91_pmc *pmc = plat->reg_base; in at91_plladiv_clk_get_rate() local
32 if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2) in at91_plladiv_clk_get_rate()
41 struct at91_pmc *pmc = plat->reg_base; in at91_plladiv_clk_set_rate() local
55 writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2), in at91_plladiv_clk_set_rate()
56 &pmc->mckr); in at91_plladiv_clk_set_rate()
H A Dclk-peripheral.c57 struct at91_pmc *pmc = plat->reg_base; in periph_clk_enable() local
66 addr = &pmc->pcer; in periph_clk_enable()
68 addr = &pmc->pcer1; in periph_clk_enable()
72 writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr); in periph_clk_enable()
73 setbits_le32(&pmc->pcr, in periph_clk_enable()
H A Dclk-utmi.c25 struct at91_pmc *pmc = plat->reg_base; in utmi_clk_enable() local
33 if (readl(&pmc->sr) & AT91_PMC_LOCKU) in utmi_clk_enable()
83 tmp = readl(&pmc->uckr); in utmi_clk_enable()
87 writel(tmp, &pmc->uckr); in utmi_clk_enable()
89 while ((--timeout) && !(readl(&pmc->sr) & AT91_PMC_LOCKU)) in utmi_clk_enable()
H A Dclk-system.c73 struct at91_pmc *pmc = plat->reg_base; in system_clk_enable() local
81 writel(mask, &pmc->scer); in system_clk_enable()
91 while (!(readl(&pmc->sr) & mask)) in system_clk_enable()
H A Dclk-usb.c26 struct at91_pmc *pmc = plat->reg_base; in at91_usb_clk_get_rate() local
32 tmp = readl(&pmc->pcr); in at91_usb_clk_get_rate()
47 struct at91_pmc *pmc = plat->reg_base; in at91_usb_clk_set_rate() local
97 writel(tmp, &pmc->usb); in at91_usb_clk_set_rate()
H A Dclk-plla.c19 struct at91_pmc *pmc = plat->reg_base; in plla_clk_enable() local
21 if (readl(&pmc->sr) & AT91_PMC_LOCKA) in plla_clk_enable()
H A Dclk-main.c19 struct at91_pmc *pmc = plat->reg_base; in main_osc_clk_enable() local
21 if (readl(&pmc->sr) & AT91_PMC_MOSCSELS) in main_osc_clk_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dwarmboot_avp.c26 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in wb_start() local
67 if (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) { in wb_start()
69 writel(reg, &pmc->pmc_pwrgate_toggle); in wb_start()
70 while (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) in wb_start()
75 reg = readl(&pmc->pmc_remove_clamping); in wb_start()
77 writel(reg, &pmc->pmc_remove_clamping); in wb_start()
99 reg = readl(&pmc->pmc_scratch41); in wb_start()
142 writel(reg, &pmc->pmc_scratch1); in wb_start()
146 scratch3.word = readl(&pmc->pmc_scratch3); in wb_start()
H A Dcpu.c14 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail() local
17 reg = readl(&pmc->pmc_cntrl); in enable_cpu_power_rail()
19 writel(reg, &pmc->pmc_cntrl); in enable_cpu_power_rail()
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dcpu.c302 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in is_cpu_powered() local
304 return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; in is_cpu_powered()
309 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in remove_cpu_io_clamps() local
314 reg = readl(&pmc->pmc_remove_clamping); in remove_cpu_io_clamps()
316 writel(reg, &pmc->pmc_remove_clamping); in remove_cpu_io_clamps()
324 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in powerup_cpu() local
331 reg = readl(&pmc->pmc_pwrgate_toggle); in powerup_cpu()
334 writel(reg, &pmc->pmc_pwrgate_toggle); in powerup_cpu()
H A Dcmd_enterrcm.c34 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in do_enterrcm() local
39 pmc->pmc_scratch0 = 2; in do_enterrcm()
/openbmc/u-boot/board/atmel/sama5d2_xplained/
H A Dsama5d2_xplained.c140 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in mem_init() local
148 writel(AT91_PMC_DDR, &pmc->scer); in mem_init()
168 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in at91_pmc_init() local
187 writel(0x0 << 8, &pmc->pllicpr); in at91_pmc_init()

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