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Searched refs:pllreg (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/arch/arm/mach-s5pc1xx/
H A Dclock.c25 static unsigned long s5pc100_get_pll_clk(int pllreg) in s5pc100_get_pll_clk() argument
32 switch (pllreg) { in s5pc100_get_pll_clk()
46 printf("Unsupported PLL (%d)\n", pllreg); in s5pc100_get_pll_clk()
56 if (pllreg == APLL) in s5pc100_get_pll_clk()
76 static unsigned long s5pc110_get_pll_clk(int pllreg) in s5pc110_get_pll_clk() argument
83 switch (pllreg) { in s5pc110_get_pll_clk()
97 printf("Unsupported PLL (%d)\n", pllreg); in s5pc110_get_pll_clk()
107 if (pllreg == APLL || pllreg == MPLL) in s5pc110_get_pll_clk()
120 if (pllreg == APLL) { in s5pc110_get_pll_clk()
297 unsigned long get_pll_clk(int pllreg) in get_pll_clk() argument
[all …]
/openbmc/qemu/hw/misc/
H A Dimx_ccm.c48 uint32_t imx_ccm_calc_pll(uint32_t pllreg, uint32_t base_freq) in imx_ccm_calc_pll() argument
51 int32_t mfn = MFN(pllreg); /* Numerator */ in imx_ccm_calc_pll()
52 uint32_t mfi = MFI(pllreg); /* Integer part */ in imx_ccm_calc_pll()
53 uint32_t mfd = 1 + MFD(pllreg); /* Denominator */ in imx_ccm_calc_pll()
54 uint32_t pd = 1 + PD(pllreg); /* Pre-divider */ in imx_ccm_calc_pll()
67 DPRINTF("(pllreg = 0x%08x, base_freq = %u) = %d\n", pllreg, base_freq, in imx_ccm_calc_pll()
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock.c113 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) in exynos_get_pll_clk() argument
125 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL || in exynos_get_pll_clk()
126 pllreg == SPLL) in exynos_get_pll_clk()
140 if (pllreg == EPLL || pllreg == RPLL) { in exynos_get_pll_clk()
144 } else if (pllreg == VPLL) { in exynos_get_pll_clk()
185 static unsigned long exynos4_get_pll_clk(int pllreg) in exynos4_get_pll_clk() argument
191 switch (pllreg) { in exynos4_get_pll_clk()
207 printf("Unsupported PLL (%d)\n", pllreg); in exynos4_get_pll_clk()
211 return exynos_get_pll_clk(pllreg, r, k); in exynos4_get_pll_clk()
215 static unsigned long exynos4x12_get_pll_clk(int pllreg) in exynos4x12_get_pll_clk() argument
[all …]
/openbmc/linux/sound/pci/pcxhr/
H A Dpcxhr_mix22.c311 unsigned int *pllreg, in hr222_pll_freq_register() argument
321 *pllreg = reg + 0xC00; in hr222_pll_freq_register()
323 *pllreg = reg + 0x800; in hr222_pll_freq_register()
325 *pllreg = reg & 0x1ff; in hr222_pll_freq_register()
327 *pllreg = ((reg >> 1) & 0x1ff) + 0x200; in hr222_pll_freq_register()
330 *pllreg = ((reg >> 2) & 0x1ff) + 0x400; in hr222_pll_freq_register()
342 unsigned int speed, pllreg = 0; in hr222_sub_set_clock() local
348 err = hr222_pll_freq_register(rate, &pllreg, &realfreq); in hr222_sub_set_clock()
372 PCXHR_OUTPB(mgr, PCXHR_XLX_HIFREQ, pllreg >> 8); in hr222_sub_set_clock()
373 PCXHR_OUTPB(mgr, PCXHR_XLX_LOFREQ, pllreg & 0xff); in hr222_sub_set_clock()
[all …]
H A Dpcxhr.c183 static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg, in pcxhr_pll_freq_register() argument
193 *pllreg = reg + 0x800; in pcxhr_pll_freq_register()
195 *pllreg = reg & 0x1ff; in pcxhr_pll_freq_register()
197 *pllreg = ((reg >> 1) & 0x1ff) + 0x200; in pcxhr_pll_freq_register()
200 *pllreg = ((reg >> 2) & 0x1ff) + 0x400; in pcxhr_pll_freq_register()
237 unsigned int val, realfreq, pllreg; in pcxhr_get_clock_reg() local
263 err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq); in pcxhr_get_clock_reg()
268 rmh.cmd[1] = pllreg & MASK_DSP_WORD; in pcxhr_get_clock_reg()
269 rmh.cmd[2] = pllreg >> 24; in pcxhr_get_clock_reg()
/openbmc/linux/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c234 u32 pllreg = 0; in format_pll_reg() local
243 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_BYPASS, 0); in format_pll_reg()
244 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POWER, 1); in format_pll_reg()
245 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_INPUT, 0); in format_pll_reg()
246 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD); in format_pll_reg()
247 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD); in format_pll_reg()
248 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N); in format_pll_reg()
249 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M); in format_pll_reg()
251 return pllreg; in format_pll_reg()
/openbmc/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c26 static ulong get_PLLCLK(uint32_t *pllreg) in get_PLLCLK() argument
29 const uint32_t clkset = readl(pllreg); in get_PLLCLK()
/openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/
H A Dclk.h17 unsigned long get_pll_clk(int pllreg);
/openbmc/qemu/include/hw/misc/
H A Dimx_ccm.h59 uint32_t imx_ccm_calc_pll(uint32_t pllreg, uint32_t base_freq);
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dclk.h37 unsigned long get_pll_clk(int pllreg);
/openbmc/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c475 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; in nv_load_state_ramdac() local
481 clk->pll_prog(clk, pllreg, &regp->pllvals); in nv_load_state_ramdac()