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Searched refs:pllp (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/drivers/clk/
H A Dclk_stm32f.c401 u16 pllm, plln, pllp, pllq; in stm32_clk_get_rate() local
408 pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) in stm32_clk_get_rate()
413 sysclk = vco / pllp; in stm32_clk_get_rate()
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra210.c1295 static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp) in tegra210_pllp_set_defaults() argument
1298 u32 val = readl_relaxed(clk_base + pllp->params->base_reg); in tegra210_pllp_set_defaults()
1300 pllp->params->defaults_set = true; in tegra210_pllp_set_defaults()
1308 pllp_check_defaults(pllp, true); in tegra210_pllp_set_defaults()
1309 if (!pllp->params->defaults_set) in tegra210_pllp_set_defaults()
1313 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1317 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1325 clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1328 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
1332 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
/openbmc/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Dreg.h6267 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN);
6273 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12);
6279 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8);
6285 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4);
6291 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4);
6295 MLXSW_REG_ZERO(pllp, payload); in mlxsw_reg_pllp_pack()
12987 MLXSW_REG(pllp),
H A Dspectrum.c1598 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pllp), pllp_pl); in mlxsw_sp_port_label_info_get()