Searched refs:pllinfo (Results 1 – 7 of 7) sorted by relevance
102 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask; in clock_ll_read_pll()103 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask; in clock_ll_read_pll()104 *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask; in clock_ll_read_pll()107 *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask; in clock_ll_read_pll()108 *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask; in clock_ll_read_pll()142 misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift); in clock_start_pll()144 misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift); in clock_start_pll()552 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask; in clock_get_rate()599 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift); in clock_set_rate()602 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift); in clock_set_rate()[all …]
173 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; in pllx_set_rate() local187 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift); in pllx_set_rate()188 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); in pllx_set_rate()193 reg = (cpcon << pllinfo->kcp_shift); in pllx_set_rate()214 if (pllinfo->lock_ena < 32) in pllx_set_rate()215 reg |= (1 << pllinfo->lock_ena); in pllx_set_rate()
658 struct clk_pll_info *pllinfo; in clock_early_init() local664 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()701 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()702 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()706 pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; in clock_early_init()707 data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift); in clock_early_init()708 data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena); in clock_early_init()
54 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; in enable_cpu_clocks() local62 } while ((reg & (1 << pllinfo->lock_det)) == 0); in enable_cpu_clocks()
838 struct clk_pll_info *pllinfo; in clock_early_init() local844 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()881 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()882 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()886 pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; in clock_early_init()887 data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift); in clock_early_init()888 data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena); in clock_early_init()
47 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; in enable_cpu_clocks() local56 } while ((reg & (1 << pllinfo->lock_det)) == 0); in enable_cpu_clocks()
973 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; in clock_early_init() local1028 data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena); in clock_early_init()