Searched refs:pll_reg_base (Results 1 – 1 of 1) sorted by relevance
| /openbmc/u-boot/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 77 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) in ar934x_srif_pll_cfg() argument
81 writel(0x10810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
82 writel(srif_val, pll_reg_base + 0x0); in ar934x_srif_pll_cfg()
83 writel(0xd0810f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
84 writel(0x03000000, pll_reg_base + 0x8); in ar934x_srif_pll_cfg()
85 writel(0xd0800f00, pll_reg_base + 0x4); in ar934x_srif_pll_cfg()
87 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
89 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
92 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0); in ar934x_srif_pll_cfg()
94 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
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