Home
last modified time | relevance | path

Searched refs:pll5_cfg (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c246 reg_val = readl(&ccm->pll5_cfg); in mctl_setup_dram_clock()
288 writel(reg_val, &ccm->pll5_cfg); in mctl_setup_dram_clock()
291 setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK); in mctl_setup_dram_clock()
H A Dclock_sun8i_a83t.c117 div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg); in clock_set_pll5()
H A Ddram_sun50i_h6.c305 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
312 CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg); in mctl_sys_init()
313 mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK); in mctl_sys_init()
H A Dclock_sun4i.c210 uint32_t rval = readl(&ccm->pll5_cfg); in clock_get_pll5p()
H A Dclock_sun6i.c211 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); in clock_set_pll5()
H A Ddram_sun8i_a83t.c399 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
H A Ddram_sunxi_dw.c375 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun8i_a83t.h25 u32 pll5_cfg; /* 0x20 pll5 ddr control */ member
H A Dclock_sun4i.h22 u32 pll5_cfg; /* 0x20 pll5 control */ member
H A Dclock_sun50i_h6.h15 u32 pll5_cfg; /* 0x010 pll5 (ddr) control */ member
H A Dclock_sun6i.h22 u32 pll5_cfg; /* 0x20 pll5 control */ member