Searched refs:pll5_cfg (Results 1 – 11 of 11) sorted by relevance
/openbmc/u-boot/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 246 reg_val = readl(&ccm->pll5_cfg); in mctl_setup_dram_clock() 288 writel(reg_val, &ccm->pll5_cfg); in mctl_setup_dram_clock() 291 setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK); in mctl_setup_dram_clock()
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H A D | clock_sun8i_a83t.c | 117 div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg); in clock_set_pll5()
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H A D | dram_sun50i_h6.c | 305 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init() 312 CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg); in mctl_sys_init() 313 mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK); in mctl_sys_init()
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H A D | clock_sun4i.c | 210 uint32_t rval = readl(&ccm->pll5_cfg); in clock_get_pll5p()
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H A D | clock_sun6i.c | 211 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); in clock_set_pll5()
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H A D | dram_sun8i_a83t.c | 399 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
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H A D | dram_sunxi_dw.c | 375 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
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/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
H A D | clock_sun8i_a83t.h | 25 u32 pll5_cfg; /* 0x20 pll5 ddr control */ member
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H A D | clock_sun4i.h | 22 u32 pll5_cfg; /* 0x20 pll5 control */ member
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H A D | clock_sun50i_h6.h | 15 u32 pll5_cfg; /* 0x010 pll5 (ddr) control */ member
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H A D | clock_sun6i.h | 22 u32 pll5_cfg; /* 0x20 pll5 control */ member
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