| /openbmc/u-boot/arch/arm/mach-keystone/ |
| H A D | clock.c | 46 if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK)) in wait_for_completion()
53 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK | in bypass_main_pll()
68 if (data->pll == MAIN_PLL) in configure_mult_div()
69 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); in configure_mult_div()
71 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, in configure_mult_div()
77 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, in configure_mult_div()
82 clrsetbits_le32(keystone_pll_regs[data->pll].reg1, in configure_mult_div()
86 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, in configure_mult_div()
100 tmp = pllctl_reg_read(data->pll, secctl); in configure_main_pll()
104 setbits_le32(keystone_pll_regs[data->pll].reg1, in configure_main_pll()
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| H A D | cmd_clock.c | 16 .pll = MAIN_PLL,
28 cmd_pll_data.pll = PASS_PLL; in do_pll_cmd()
31 cmd_pll_data.pll = TETRIS_PLL; in do_pll_cmd()
35 cmd_pll_data.pll = DDR3A_PLL; in do_pll_cmd()
37 cmd_pll_data.pll = DDR3B_PLL; in do_pll_cmd()
40 cmd_pll_data.pll = DDR3_PLL; in do_pll_cmd()
50 cmd_pll_data.pll, cmd_pll_data.pll_m, in do_pll_cmd()
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| /openbmc/u-boot/arch/m68k/cpu/mcf5445x/ |
| H A D | speed.c | 59 pll_t *pll = (pll_t *)MMAP_PLL; in clock_exit_limp() local
65 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) in clock_exit_limp()
73 pll_t *pll = (pll_t *)MMAP_PLL; in setup_5441x_clocks() local
80 out_be32(&pll->pcr, 0x00000013); in setup_5441x_clocks()
81 out_be32(&pll->pdr, 0x00e70c61); in setup_5441x_clocks()
92 temp = in_be32(&pll->pcr); in setup_5441x_clocks()
95 out_be32(&pll->pcr, temp); in setup_5441x_clocks()
97 temp = in_be32(&pll->pdr); in setup_5441x_clocks()
100 out_be32(&pll->pdr, temp); in setup_5441x_clocks()
106 vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) * in setup_5441x_clocks()
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mtk.c | 82 static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll, in __mtk_pll_recalc_rate() argument
85 int pcwbits = pll->pcwbits; in __mtk_pll_recalc_rate()
115 const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; in mtk_pll_set_rate_regs() local
119 val = readl(priv->base + pll->pd_reg); in mtk_pll_set_rate_regs()
120 val &= ~(POSTDIV_MASK << pll->pd_shift); in mtk_pll_set_rate_regs()
121 val |= (ffs(postdiv) - 1) << pll->pd_shift; in mtk_pll_set_rate_regs()
124 if (pll->pd_reg != pll->pcw_reg) { in mtk_pll_set_rate_regs()
125 writel(val, priv->base + pll->pd_reg); in mtk_pll_set_rate_regs()
126 val = readl(priv->base + pll->pcw_reg); in mtk_pll_set_rate_regs()
130 val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift); in mtk_pll_set_rate_regs()
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| /openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/ |
| H A D | generic.c | 26 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) in imx_decode_pll() argument
28 unsigned int mfi = (pll >> 10) & 0xf; in imx_decode_pll()
29 unsigned int mfn = pll & 0x3ff; in imx_decode_pll()
30 unsigned int mfd = (pll >> 16) & 0x3ff; in imx_decode_pll()
31 unsigned int pd = (pll >> 26) & 0xf; in imx_decode_pll()
46 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in clk_in_26m() local
48 if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) { in clk_in_26m()
58 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_mpllclk() local
59 ulong cscr = readl(&pll->cscr); in imx_get_mpllclk()
67 return imx_decode_pll(readl(&pll->mpctl0), fref); in imx_get_mpllclk()
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| H A D | timer.c | 91 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in timer_init() local
96 writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0); in timer_init()
97 writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1); in timer_init()
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| /openbmc/u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | clock_defs.h | 53 #define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) argument
54 #define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) argument
55 #define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) argument
57 #define pllctl_reg_rmw(pll, reg, mask, val) \ argument
58 pllctl_reg_write(pll, reg, \
59 (pllctl_reg_read(pll, reg) & ~(mask)) | val)
61 #define pllctl_reg_setbits(pll, reg, mask) \ argument
62 pllctl_reg_rmw(pll, reg, 0, mask)
64 #define pllctl_reg_clrbits(pll, reg, mask) \ argument
65 pllctl_reg_rmw(pll, reg, mask, 0)
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| /openbmc/u-boot/arch/arm/include/asm/arch-s32v234/ |
| H A D | mc_cgm_regs.h | 70 #define PLLDIG_PLLDV(pll) ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80)) argument
94 #define PLLDIG_PLLFD(pll) ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80)) argument
100 #define PLLDIG_PLLCAL1(pll) ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80)) argument
110 #define DFS_DLLPRG1(pll) (DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80)) argument
137 #define DFS_CTRL(pll) (DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80)) argument
142 #define DFS_PORTSR(pll) (DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80)) argument
144 #define DFS_PORTRESET(pll) (DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80)) argument
151 #define DFS_DVPORTn(pll,n) (DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4))) argument
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| /openbmc/u-boot/arch/m68k/cpu/mcf5227x/ |
| H A D | speed.c | 57 pll_t *pll = (pll_t *)MMAP_PLL; in clock_exit_limp() local
63 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) in clock_exit_limp()
74 pll_t *pll = (pll_t *)MMAP_PLL; in get_clocks() local
78 pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF; in get_clocks()
90 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
93 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); in get_clocks()
95 out_be32(&pll->pcr, pcrvalue); in get_clocks()
97 ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * in get_clocks()
103 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
112 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1; in get_clocks()
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| /openbmc/u-boot/board/freescale/s32v234evb/ |
| H A D | clock.c | 17 static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq) in select_pll_source_clk() argument
39 switch (pll) { in select_pll_source_clk()
50 pll_idx = pll; in select_pll_source_clk()
81 static int program_pll(enum pll_type pll, u32 refclk_freq, u32 freq0, u32 freq1, in program_pll() argument
103 if (select_pll_source_clk(pll, refclk_freq) < 0) { in program_pll()
114 PLLDIG_PLLDV_MFD(plldv_mfd), PLLDIG_PLLDV(pll)); in program_pll()
116 writel(readl(PLLDIG_PLLFD(pll)) | PLLDIG_PLLFD_MFN_SET(pllfd_mfn) | in program_pll()
117 PLLDIG_PLLFD_SMDEN, PLLDIG_PLLFD(pll)); in program_pll()
120 writel(readl(MC_ME_RUNn_MC(0)) | MC_ME_RUNMODE_MC_PLL(pll), in program_pll()
126 if ((pll == ARM_PLL) || (pll == ENET_PLL) || (pll == DDR_PLL)) { in program_pll()
[all …]
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| /openbmc/u-boot/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 21 pll_t *pll = (pll_t *) MMAP_PLL; in get_clocks() local
23 out_8(&pll->odr, CONFIG_SYS_PLL_ODR); in get_clocks()
24 out_8(&pll->fdr, CONFIG_SYS_PLL_FDR); in get_clocks()
57 pll_t *pll = (pll_t *)(MMAP_PLL); in get_clocks() local
60 out_be32(&pll->syncr, 0x01080000); in get_clocks()
61 while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) in get_clocks()
63 out_be32(&pll->syncr, 0x01000000); in get_clocks()
64 while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) in get_clocks()
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| /openbmc/u-boot/arch/m68k/cpu/mcf532x/ |
| H A D | speed.c | 53 pll_t *pll = (pll_t *)(MMAP_PLL); in get_sys_clock() local
67 u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; in get_sys_clock()
68 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); in get_sys_clock()
69 u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1; in get_sys_clock()
74 return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4); in get_sys_clock()
144 pll_t *pll = (pll_t *)(MMAP_PLL); in clock_pll() local
153 u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1; in clock_pll()
154 mfd = (in_be32(&pll->pcr) & 0x3F) + 1; in clock_pll()
159 mfd = in_8(&pll->pfdr); in clock_pll()
211 out_be32(&pll->pdr, in clock_pll()
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| /openbmc/u-boot/arch/mips/mach-ath79/qca953x/ |
| H A D | clk.c | 34 u32 val, ctrl, xtal, pll, div; in get_clocks() local
46 pll = xtal / div; in get_clocks()
51 pll *= div; in get_clocks()
56 pll >>= div; in get_clocks()
61 gd->cpu_clk = pll / div; in get_clocks()
68 pll = xtal / div; in get_clocks()
73 pll *= div; in get_clocks()
78 pll >>= div; in get_clocks()
83 gd->mem_clk = pll / div; in get_clocks()
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| /openbmc/u-boot/drivers/video/sunxi/ |
| H A D | sunxi_dw_hdmi.c | 31 u32 pll; member
94 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_init()
98 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_init()
101 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_init()
102 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_init()
148 writel(0x30dc5fc0, &phy->pll); in sunxi_dw_hdmi_phy_set()
152 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
155 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
157 setbits_le32(&phy->pll, tmp + 2); in sunxi_dw_hdmi_phy_set()
159 setbits_le32(&phy->pll, 0x3f); in sunxi_dw_hdmi_phy_set()
[all …]
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| /openbmc/u-boot/arch/mips/mach-ath79/ar933x/ |
| H A D | clk.c | 34 u32 val, xtal, pll, div; in get_clocks() local
44 pll = xtal / div; in get_clocks()
49 pll *= div; in get_clocks()
54 pll >>= div; in get_clocks()
61 gd->cpu_clk = pll / div; in get_clocks()
66 gd->mem_clk = pll / div; in get_clocks()
71 gd->bus_clk = pll / div; in get_clocks()
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| /openbmc/u-boot/arch/arm/mach-uniphier/clk/ |
| H A D | Makefile | 14 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o
15 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o
16 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o
20 obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o
21 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o
22 obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += clk-pxs3.o pll-pxs3.o
26 obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o
27 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o
28 obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += pll-base-ld20.o
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| /openbmc/u-boot/arch/arm/cpu/armv7/iproc-common/ |
| H A D | armpll.c | 41 uint32_t pll; in armpll_config() local
96 pll = readl(IHOST_PROC_CLK_PLLARMB); in armpll_config()
97 pll &= ~((1 << IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH) - 1); in armpll_config()
102 pll |= ndiv_frac; in armpll_config()
103 writel(pll, IHOST_PROC_CLK_PLLARMB); in armpll_config()
125 pll = readl(IHOST_PROC_CLK_PLLARMA); in armpll_config()
126 pll |= (1 << IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB); in armpll_config()
127 writel(pll, IHOST_PROC_CLK_PLLARMA); in armpll_config()
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| /openbmc/u-boot/arch/arm/mach-tegra/ |
| H A D | clock.c | 92 struct clk_pll *pll = get_pll(clkid); in clock_ll_read_pll() local
101 data = readl(&pll->pll_base); in clock_ll_read_pll()
105 data = readl(&pll->pll_misc); in clock_ll_read_pll()
116 struct clk_pll *pll = NULL; in clock_start_pll() local
122 pll = get_pll(clkid); in clock_start_pll()
138 if (pll) in clock_start_pll()
139 misc_data = readl(&pll->pll_misc); in clock_start_pll()
151 if (pll) { in clock_start_pll()
152 writel(misc_data, &pll->pll_misc); in clock_start_pll()
153 writel(data, &pll->pll_base); in clock_start_pll()
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| H A D | cpu.c | 170 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, in pllx_set_rate() argument
179 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) { in pllx_set_rate()
189 writel(reg, &pll->pll_base); in pllx_set_rate()
204 writel(reg, &pll->pll_misc); in pllx_set_rate()
207 reg = readl(&pll->pll_base); in pllx_set_rate()
209 writel(reg, &pll->pll_base); in pllx_set_rate()
213 reg = readl(&pll->pll_misc); in pllx_set_rate()
216 writel(reg, &pll->pll_misc); in pllx_set_rate()
220 reg = readl(&pll->pll_base); in pllx_set_rate()
222 writel(reg, &pll->pll_base); in pllx_set_rate()
[all …]
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| /openbmc/u-boot/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 160 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq) in decode_pll() argument
166 ctrl = readl(&pll->ctrl); in decode_pll()
169 mfn = readl(&pll->hfs_mfn); in decode_pll()
170 mfd = readl(&pll->hfs_mfd); in decode_pll()
171 op = readl(&pll->hfs_op); in decode_pll()
173 mfn = readl(&pll->mfn); in decode_pll()
174 mfd = readl(&pll->mfd); in decode_pll()
175 op = readl(&pll->op); in decode_pll()
551 static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll) in calc_pll_params() argument
607 pll->pd = (u32)pd; in calc_pll_params()
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| /openbmc/u-boot/arch/arm/cpu/armv8/s32v234/ |
| H A D | generic.c | 27 static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv, in get_pllfreq() argument
55 if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) { in get_pllfreq()
57 readl(DFS_DVPORTn(pll, selected_output - 1)); in get_pllfreq()
82 static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq, in decode_pll() argument
87 plldv = readl(PLLDIG_PLLDV(pll)); in decode_pll()
88 pllfd = readl(PLLDIG_PLLFD(pll)); in decode_pll()
90 return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output); in decode_pll()
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| /openbmc/u-boot/arch/m68k/cpu/mcf523x/ |
| H A D | speed.c | 23 pll_t *pll = (pll_t *)(MMAP_PLL); in get_clocks() local
25 out_be32(&pll->syncr, PLL_SYNCR_MFD(1)); in get_clocks()
27 while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK)) in get_clocks()
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| /openbmc/u-boot/drivers/clk/ |
| H A D | clk_zynqmp.c | 372 enum zynqmp_clk pll; in zynqmp_clk_get_cpu_rate() local
384 pll = zynqmp_clk_get_cpu_pll(clk_ctrl); in zynqmp_clk_get_cpu_rate()
385 pllrate = zynqmp_clk_get_pll_rate(priv, pll); in zynqmp_clk_get_cpu_rate()
395 enum zynqmp_clk pll; in zynqmp_clk_get_ddr_rate() local
407 pll = zynqmp_clk_get_ddr_pll(clk_ctrl); in zynqmp_clk_get_ddr_rate()
408 pllrate = zynqmp_clk_get_pll_rate(priv, pll); in zynqmp_clk_get_ddr_rate()
418 enum zynqmp_clk pll; in zynqmp_clk_get_peripheral_rate() local
440 pll = zynqmp_clk_get_peripheral_pll(clk_ctrl); in zynqmp_clk_get_peripheral_rate()
441 pllrate = zynqmp_clk_get_pll_rate(priv, pll); in zynqmp_clk_get_peripheral_rate()
453 enum zynqmp_clk pll; in zynqmp_clk_get_wdt_rate() local
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| /openbmc/qemu/hw/misc/ |
| H A D | bcm2835_cprman.c | 67 static bool pll_is_locked(const CprmanPllState *pll) in pll_is_locked() argument
69 return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN) in pll_is_locked()
70 && !FIELD_EX32(*pll->reg_cm, CM_PLLx, ANARST); in pll_is_locked()
73 static void pll_update(CprmanPllState *pll) in pll_update() argument
77 if (!pll_is_locked(pll)) { in pll_update()
78 clock_update(pll->out, 0); in pll_update()
82 pdiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PDIV); in pll_update()
85 clock_update(pll->out, 0); in pll_update()
89 ndiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, NDIV); in pll_update()
90 fdiv = FIELD_EX32(*pll->reg_a2w_frac, A2W_PLLx_FRAC, FRAC); in pll_update()
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| H A D | stm32l4x5_rcc.c | 203 static void pll_update(RccPllState *pll, bool bypass_source) in pll_update() argument
209 vco_freq = muldiv64(clock_get_hz(pll->in), pll->vco_multiplier, 1); in pll_update()
212 if (!pll->channel_exists[i]) { in pll_update()
216 old_channel_freq = clock_get_hz(pll->channels[i]); in pll_update()
218 !pll->enabled || in pll_update()
219 !pll->channel_enabled[i] || in pll_update()
220 !pll->channel_divider[i]) { in pll_update()
225 pll->channel_divider[i]); in pll_update()
233 clock_update_hz(pll->channels[i], channel_freq); in pll_update()
234 trace_stm32l4x5_rcc_pll_update(pll->id, i, vco_freq, in pll_update()
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