| /openbmc/u-boot/drivers/video/tegra124/ |
| H A D | display.c | 28 int pclk = timing->pixelclock.typ; in tegra_dc_calc_refresh()
49 refresh % 1000, timing->pixelclock.typ); in print_mode()
92 timing->pixelclock.typ, shift_clock_div); in update_display_mode()
308 printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ); in dump_config()
378 plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2); in display_init()
382 } else if (plld_rate != timing->pixelclock.typ * 2) { in display_init()
384 timing->pixelclock.typ = plld_rate / 2; in display_init()
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| H A D | dp.c | 507 if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ || in tegra_dc_dp_calc_config()
511 if ((u64)timing->pixelclock.typ * link_cfg->bits_per_pixel >= in tegra_dc_dp_calc_config()
516 timing->pixelclock.typ)); in tegra_dc_dp_calc_config()
518 ratio_f = (u64)timing->pixelclock.typ * link_cfg->bits_per_pixel * f; in tegra_dc_dp_calc_config()
621 link_rate, timing->pixelclock.typ) - in tegra_dc_dp_calc_config()
637 * link_rate, timing->pixelclock.typ) - (36 / in tegra_dc_dp_calc_config()
1355 if (!timing->pixelclock.typ || !timing->hactive.typ || in tegra_dc_dp_explore_link_cfg()
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| /openbmc/u-boot/drivers/video/ |
| H A D | atmel_lcdfb.c | 140 value = get_lcdc_clk_rate(0) / timing->pixelclock.typ; in atmel_fb_init()
141 if (get_lcdc_clk_rate(0) % timing->pixelclock.typ) in atmel_fb_init()
218 timing.pixelclock.typ = panel_info.vl_clk; in lcd_ctrl_init()
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| H A D | dw_hdmi.c | 972 edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ); in dw_hdmi_enable()
976 ret = hdmi->phy_set(hdmi, edid->pixelclock.typ); in dw_hdmi_enable()
985 hdmi_audio_set_samplerate(hdmi, edid->pixelclock.typ); in dw_hdmi_enable()
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| H A D | atmel_hlcdfb.c | 325 value = priv->clk_rate / timing->pixelclock.typ; in atmel_hlcdc_init()
326 if (priv->clk_rate % timing->pixelclock.typ) in atmel_hlcdc_init()
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| H A D | mali_dp.c | 187 if (clk_set_rate(&malidp->pxlclk, timings->pixelclock.typ) == 0) in malidp_setup_mode()
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| H A D | tegra.c | 368 priv->pixel_clock = timing->pixelclock.typ; in tegra_lcd_ofdata_to_platdata()
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| H A D | tda19988.c | 372 u8 div = 148500000 / timing->pixelclock.typ, reg; in tda19988_enable()
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| /openbmc/u-boot/drivers/video/stm32/ |
| H A D | stm32_ltdc.c | 388 rate = clk_set_rate(&pclk, priv->timing.pixelclock.typ); in stm32_ltdc_probe()
391 __func__, priv->timing.pixelclock.typ, rate); in stm32_ltdc_probe()
396 priv->timing.pixelclock.typ, rate); in stm32_ltdc_probe()
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| /openbmc/u-boot/drivers/video/sunxi/ |
| H A D | sunxi_lcd.c | 55 lcdc_pll_set(ccm, 0, edid->pixelclock.typ / 1000, in sunxi_lcd_enable()
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| H A D | sunxi_dw_hdmi.c | 257 int div = clock_get_pll3() / edid->pixelclock.typ; in sunxi_dw_hdmi_lcdc_init()
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| H A D | sunxi_display.c | 618 timing->pixelclock.typ = mode->pixclock_khz * 1000; in sunxi_ctfb_mode_to_display_timing()
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| /openbmc/u-boot/drivers/video/rockchip/ |
| H A D | rk3288_mipi.c | 93 priv->pix_clk = timing->pixelclock.typ; in rk_mipi_enable()
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| H A D | rk3399_mipi.c | 85 priv->pix_clk = timing->pixelclock.typ; in rk_display_enable()
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| H A D | rk_vop.c | 307 ret = clk_set_rate(&clk, timing.pixelclock.typ); in rk_display_init()
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| /openbmc/u-boot/common/ |
| H A D | edid.c | 90 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); in decode_timing()
130 timing->pixelclock.typ, in decode_timing()
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| /openbmc/u-boot/include/ |
| H A D | fdtdec.h | 888 struct timing_entry pixelclock; member
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| /openbmc/u-boot/drivers/video/meson/ |
| H A D | meson_vclk.c | 889 vclk_freq = mode->pixelclock.typ / 1000; in meson_vpu_setup_vclk()
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| /openbmc/u-boot/drivers/core/ |
| H A D | ofnode.c | 483 ret |= decode_timing_property(node, "clock-frequency", &dt->pixelclock); in ofnode_decode_display_timing()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | da850.dtsi | 896 max-pixelclock = <37500>;
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| /openbmc/u-boot/lib/ |
| H A D | fdtdec.c | 1057 &dt->pixelclock); in fdtdec_decode_display_timing()
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