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Searched refs:phy_write (Results 1 – 25 of 139) sorted by relevance

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/openbmc/u-boot/cmd/aspeed/nettest/
H A Dphy.c66 void phy_write (MAC_ENGINE *eng, int index, uint32_t data) in phy_write() function
199 phy_write(eng, adr, ((phy_read(eng, adr) & (~clr_mask)) | set_mask)); in phy_clrset()
345 phy_write(eng, 9, eng->phy.PHY_09h); in recov_phy_marvell()
349 phy_write(eng, 29, 0x0007); in recov_phy_marvell()
351 phy_write(eng, 29, 0x0010); in recov_phy_marvell()
353 phy_write(eng, 29, 0x0012); in recov_phy_marvell()
356 phy_write(eng, 18, eng->phy.PHY_12h); in recov_phy_marvell()
374 phy_write( eng, 18, 0x0000 ); in phy_marvell()
381 phy_write( eng, 29, 0x0007 ); in phy_marvell()
383 phy_write( eng, 29, 0x0010 ); in phy_marvell()
[all …]
/openbmc/linux/drivers/net/phy/
H A Dvitesse.c99 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon); in vsc824x_add_skew()
108 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, in vsc824x_config_init()
134 phy_write(phydev, 0x1f, 0x2a30); in vsc73xx_config_init()
136 phy_write(phydev, 0x1f, 0x0000); in vsc73xx_config_init()
150 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
152 phy_write(phydev, 0x1f, 0x52b5); in vsc738x_config_init()
153 phy_write(phydev, 0x10, 0xb68a); in vsc738x_config_init()
156 phy_write(phydev, 0x10, 0x968a); in vsc738x_config_init()
157 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
159 phy_write(phydev, 0x1f, 0x0000); in vsc738x_config_init()
[all …]
H A Dnational.c54 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_read()
60 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_write()
61 phy_write(phydev, NS_EXP_MEM_DATA, data); in ns_exp_write()
73 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7); in ns_ack_interrupt()
92 phy_write(phydev, DP83865_INT_CLEAR, irq_status & ~0x7); in ns_handle_interrupt()
108 err = phy_write(phydev, DP83865_INT_MASK, in ns_config_intr()
111 err = phy_write(phydev, DP83865_INT_MASK, 0); in ns_config_intr()
125 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN)); in ns_giga_speed_fallback()
128 phy_write(phydev, NS_EXP_MEM_CTL, 0); in ns_giga_speed_fallback()
129 phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0); in ns_giga_speed_fallback()
[all …]
H A Drockchip.c47 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
51 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_init_tstmode()
55 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
61 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_close_tstmode()
76 ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB); in rockchip_integrated_phy_analog_init()
79 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG); in rockchip_integrated_phy_analog_init()
98 ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_integrated_phy_config_init()
147 err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_set_polarity()
H A Ddavicom.c87 err = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
90 err = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
123 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_aneg()
142 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_init()
159 err = phy_write(phydev, MII_DM9161_SCR, temp); in dm9161_config_init()
164 err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT); in dm9161_config_init()
170 return phy_write(phydev, MII_BMCR, BMCR_ANENABLE); in dm9161_config_init()
H A Dmeson-gxl.c48 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
51 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
54 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
57 return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
62 phy_write(phydev, TSTCNTL, 0); in meson_gxl_close_banks()
74 ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ | in meson_gxl_read_reg()
98 ret = phy_write(phydev, TSTWRITE, value); in meson_gxl_write_reg()
102 ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE | in meson_gxl_write_reg()
H A Dmicrochip.c40 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF); in lan88xx_phy_config_intr()
42 rc = phy_write(phydev, LAN88XX_INT_MASK, in lan88xx_phy_config_intr()
46 rc = phy_write(phydev, LAN88XX_INT_MASK, 0); in lan88xx_phy_config_intr()
260 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg); in lan88xx_probe()
312 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1); in lan88xx_set_mdix()
316 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf); in lan88xx_set_mdix()
317 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0); in lan88xx_set_mdix()
358 phy_write(phydev, LAN88XX_INT_MASK, temp); in lan88xx_link_change_notify()
362 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */ in lan88xx_link_change_notify()
364 phy_write(phydev, MII_BMCR, temp); /* set to 100 later */ in lan88xx_link_change_notify()
[all …]
H A Dbcm7xxx.c79 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
107 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
265 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
270 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
280 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
336 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
340 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
346 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
350 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
355 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
[all …]
/openbmc/u-boot/drivers/net/phy/
H A Dmarvell.c111 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); in m88e1xxx_phy_extread()
113 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); in m88e1xxx_phy_extread()
123 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); in m88e1xxx_phy_extwrite()
124 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val); in m88e1xxx_phy_extwrite()
125 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); in m88e1xxx_phy_extwrite()
134 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
136 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in m88e1011s_config()
137 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); in m88e1011s_config()
138 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in m88e1011s_config()
139 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); in m88e1011s_config()
[all …]
H A Dmeson-gxl.c43 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_startup()
46 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_startup()
49 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_startup()
52 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_startup()
57 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x8D80); in meson_gxl_startup()
103 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_phy_config()
104 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_phy_config()
105 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_phy_config()
106 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_phy_config()
109 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D); in meson_gxl_phy_config()
[all …]
H A Datheros.c22 phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200); in ar8021_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in ar8021_config()
24 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); in ar8021_config()
34 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, in ar8031_config()
36 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, in ar8031_config()
42 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, in ar8031_config()
44 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, in ar8031_config()
60 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007); in ar8035_config()
61 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in ar8035_config()
62 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in ar8035_config()
[all …]
H A Dvitesse.c74 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in vitesse_config()
77 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1, in vitesse_config()
126 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in cis8204_config()
132 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
136 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
155 return phy_write(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL, ret); in vsc8601_add_skew()
175 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, in vsc8574_config()
182 phy_write(phydev, MDIO_DEVAD_NONE, in vsc8574_config()
185 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18, in vsc8574_config()
190 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19, val); in vsc8574_config()
[all …]
H A Dbroadcom.c41 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm_phy_write_misc()
46 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val); in bcm_phy_write_misc()
49 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val); in bcm_phy_write_misc()
51 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value); in bcm_phy_write_misc()
64 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm5461_config()
72 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg18); in bcm5461_config()
78 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, in bcm5461_config()
86 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, reg1c); in bcm5461_config()
167 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in bcm5482_config()
170 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm5482_config()
[all …]
H A Drealtek.c68 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr); in rtl8211f_phy_extread()
70 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage); in rtl8211f_phy_extread()
81 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr); in rtl8211f_phy_extwrite()
82 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val); in rtl8211f_phy_extwrite()
83 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage); in rtl8211f_phy_extwrite()
109 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211x_config()
114 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, in rtl8211x_config()
125 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg); in rtl8211x_config()
130 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, in rtl8211x_config()
132 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211x_config()
[all …]
H A Dti.c140 phy_write(phydev, addr, MII_MMD_CTRL, devad); in phy_read_mmd_indirect()
143 phy_write(phydev, addr, MII_MMD_DATA, prtad); in phy_read_mmd_indirect()
146 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in phy_read_mmd_indirect()
173 phy_write(phydev, addr, MII_MMD_CTRL, devad); in phy_write_mmd_indirect()
176 phy_write(phydev, addr, MII_MMD_DATA, prtad); in phy_write_mmd_indirect()
179 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in phy_write_mmd_indirect()
182 phy_write(phydev, addr, MII_MMD_DATA, data); in phy_write_mmd_indirect()
306 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, in dp83867_config()
319 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, in dp83867_config()
340 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, in dp83867_config()
[all …]
H A Dmicrel_ksz90x1.c217 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9021_phy_extended_write()
219 return phy_write(phydev, MDIO_DEVAD_NONE, in ksz9021_phy_extended_write()
226 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum); in ksz9021_phy_extended_read()
265 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000); in ksz9021_config()
290 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
293 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
296 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
299 return phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
306 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_read()
308 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_read()
[all …]
H A Daquantia.c138 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC); in aquantia_load_memory()
139 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16); in aquantia_load_memory()
140 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc); in aquantia_load_memory()
147 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW, in aquantia_load_memory()
149 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW, in aquantia_load_memory()
152 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, in aquantia_load_memory()
216 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, in aquantia_upload_firmware()
234 phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0); in aquantia_upload_firmware()
237 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, in aquantia_upload_firmware()
242 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE); in aquantia_upload_firmware()
[all …]
H A Dmscc.c660 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
863 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_pre_init()
1013 phy_write(phydev, MDIO_DEVAD_NONE, in mscc_vsc8531_vsc8541_init_scripts()
1018 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
1025 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
1026 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
1031 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
1039 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
1040 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
1045 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
[all …]
/openbmc/linux/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c285 phy_write(phydev, 0x1f, 0x0001); in rtl8168bb_hw_phy_config()
287 phy_write(phydev, 0x10, 0xf41b); in rtl8168bb_hw_phy_config()
288 phy_write(phydev, 0x1f, 0x0000); in rtl8168bb_hw_phy_config()
300 phy_write(phydev, 0x1d, 0x0f00); in rtl8168cp_1_hw_phy_config()
438 phy_write(phydev, 0x1f, 0x0005); in rtl8168d_apply_firmware_cond()
439 phy_write(phydev, 0x05, 0x001b); in rtl8168d_apply_firmware_cond()
441 phy_write(phydev, 0x1f, 0x0000); in rtl8168d_apply_firmware_cond()
455 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_common()
468 phy_write(phydev, 0x0d, val | set[i]); in rtl8168d_1_common()
481 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
[all …]
/openbmc/linux/drivers/net/ethernet/ibm/emac/
H A Dphy.c33 #define phy_write _phy_write macro
63 phy_write(phy, MII_BMCR, val); in emac_mii_reset_phy()
74 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); in emac_mii_reset_phy()
126 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
146 phy_write(phy, MII_ADVERTISE, adv); in genmii_setup_aneg()
158 phy_write(phy, MII_CTRL1000, adv); in genmii_setup_aneg()
164 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
184 phy_write(phy, MII_BMCR, ctl | BMCR_RESET); in genmii_setup_forced()
201 phy_write(phy, MII_BMCR, ctl); in genmii_setup_forced()
331 phy_write(phy, MII_CIS8201_EPCR, epcr); in cis8201_init()
[all …]
/openbmc/u-boot/board/spear/x600/
H A Dx600.c83 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); in board_phy_config()
110 phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); in board_phy_config()
116 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); in board_phy_config()
119 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); in board_phy_config()
120 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); in board_phy_config()
123 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); in board_phy_config()
126 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); in board_phy_config()
129 phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); in board_phy_config()
/openbmc/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c142 static int phy_write(struct phy *phy, u32 value, unsigned int reg) in phy_write() function
324 phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
325 phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
326 phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
327 phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
328 phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
329 phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
330 phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle); in mixel_phy_set_hs_timings()
346 phy_write(phy, CM(priv->cfg.cm), DPHY_CM); in mixel_dphy_set_pll_params()
347 phy_write(phy, CN(priv->cfg.cn), DPHY_CN); in mixel_dphy_set_pll_params()
[all …]
/openbmc/u-boot/board/Marvell/db-mv784mp-gp/
H A Ddb-mv784mp-gp.c95 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4); in board_phy_config()
97 phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140); in board_phy_config()
99 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0); in board_phy_config()
104 phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg); in board_phy_config()
107 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); in board_phy_config()
108 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); in board_phy_config()
113 phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg); in board_phy_config()
/openbmc/u-boot/board/compulab/cl-som-imx7/
H A Dcl-som-imx7.c135 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); in cl_som_imx7_rgmii_rework()
136 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); in cl_som_imx7_rgmii_rework()
137 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); in cl_som_imx7_rgmii_rework()
140 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in cl_som_imx7_rgmii_rework()
143 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in cl_som_imx7_rgmii_rework()
144 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in cl_som_imx7_rgmii_rework()
145 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in cl_som_imx7_rgmii_rework()
150 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in cl_som_imx7_rgmii_rework()
153 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in cl_som_imx7_rgmii_rework()
156 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in cl_som_imx7_rgmii_rework()
/openbmc/u-boot/board/congatec/cgtqmx6eval/
H A Dcgtqmx6eval.c336 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
337 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4); in mx6_rgmii_rework()
338 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); in mx6_rgmii_rework()
339 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000); in mx6_rgmii_rework()
341 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
342 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5); in mx6_rgmii_rework()
343 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); in mx6_rgmii_rework()
344 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG); in mx6_rgmii_rework()
346 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
347 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6); in mx6_rgmii_rework()
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