Searched refs:phy_ctl (Results 1 – 7 of 7) sorted by relevance
42 unsigned phy_ctl; in ksz90xx_startup() local49 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL); in ksz90xx_startup()51 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX) in ksz90xx_startup()56 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000) in ksz90xx_startup()58 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100) in ksz90xx_startup()60 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10) in ksz90xx_startup()
254 u16 phy_ctl = 0; in b43_generate_txhdr() local371 phy_ctl |= B43_TXH_PHY_ENC_OFDM; in b43_generate_txhdr()373 phy_ctl |= B43_TXH_PHY_ENC_CCK; in b43_generate_txhdr()375 phy_ctl |= B43_TXH_PHY_SHORTPRMBL; in b43_generate_txhdr()379 phy_ctl |= B43_TXH_PHY_ANT01AUTO; in b43_generate_txhdr()382 phy_ctl |= B43_TXH_PHY_ANT0; in b43_generate_txhdr()385 phy_ctl |= B43_TXH_PHY_ANT1; in b43_generate_txhdr()388 phy_ctl |= B43_TXH_PHY_ANT2; in b43_generate_txhdr()391 phy_ctl |= B43_TXH_PHY_ANT3; in b43_generate_txhdr()564 txhdr->phy_ctl = cpu_to_le16(phy_ctl); in b43_generate_txhdr()
29 __le16 phy_ctl; /* PHY TX control */ member
189 u16 phy_ctl = 0; in generate_txhdr_fw3() local264 phy_ctl |= B43legacy_TX4_PHY_ENC_OFDM; in generate_txhdr_fw3()266 phy_ctl |= B43legacy_TX4_PHY_SHORTPRMBL; in generate_txhdr_fw3()267 phy_ctl |= B43legacy_TX4_PHY_ANTLAST; in generate_txhdr_fw3()340 txhdr->phy_ctl = cpu_to_le16(phy_ctl); in generate_txhdr_fw3()
146 u32 val, phy_ctl; in pcie_phy_read() local154 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; in pcie_phy_read()155 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); in pcie_phy_read()
245 u32 phy_ctl; in pcie_phy_read() local253 phy_ctl = PCIE_PHY_CTRL_RD; in pcie_phy_read()254 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); in pcie_phy_read()