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Searched refs:phy0_dq (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock_init.h91 unsigned phy0_dq; member
H A Dclock_init_exynos5.c194 .phy0_dq = 0x08080808,
297 .phy0_dq = 0x08080808,
400 .phy0_dq = 0x08080808,
H A Ddmc_init_ddr3.c83 writel(mem->phy0_dq, &phy0_ctrl->phy_con6); in ddr3_mem_ctrl_init()