Searched refs:pci_get_long (Results 1 – 18 of 18) sorted by relevance
272 uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); in pcie_aer_root_get_vector()317 root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND); in pcie_aer_msg_root_port()318 prev_status = root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); in pcie_aer_msg_root_port()425 uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); in pcie_aer_update_log()447 (pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP2) & in pcie_aer_update_log()477 uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); in pcie_aer_clear_error()505 uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); in pcie_aer_record_error()512 (pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS) & (1U << fep))) { in pcie_aer_record_error()553 mask = pci_get_long(inj->aer_cap + PCI_ERR_COR_MASK); in pcie_aer_inject_cor_error()559 pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK); in pcie_aer_inject_cor_error()[all …]
152 msg.address = pci_get_long(dev->config + msi_address_lo_off(dev)); in msi_prepare_message()316 mask = pci_get_long(dev->config + in msi_is_masked()335 irq_state = pci_get_long(dev->config + msi_mask_off(dev, msi64bit)); in msi_set_mask()345 pending = pci_get_long(dev->config + msi_pending_off(dev, msi64bit)); in msi_set_mask()405 pci_get_long(dev->config + msi_address_lo_off(dev))); in msi_write_config()408 pci_get_long(dev->config + msi_address_hi_off(dev))); in msi_write_config()414 pci_get_long(dev->config + msi_mask_off(dev, msi64bit)), in msi_write_config()415 pci_get_long(dev->config + msi_pending_off(dev, msi64bit))); in msi_write_config()470 pending = pci_get_long(dev->config + msi_pending_off(dev, msi64bit)); in msi_write_config()
444 uint32_t sltcap = pci_get_long(exp_cap + PCI_EXP_SLTCAP); in pcie_cap_slot_enable_power()463 uint32_t sltcap = pci_get_long(exp_cap + PCI_EXP_SLTCAP); in pcie_cap_update_power()531 uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP); in pcie_cap_slot_plug_cb()593 uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP); in pcie_cap_slot_do_unplug()995 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & in pcie_cap_is_arifwd_enabled()1013 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); in pcie_find_capability_list()1026 header = pci_get_long(dev->config + next); in pcie_find_capability_list()1046 uint32_t header = pci_get_long(dev->config + pos); in pcie_ext_cap_set_next()
42 msg.data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA); in msix_prepare_message()95 if (xen_enabled() && xen_is_pirq_msi(pci_get_long(data))) { in msix_vector_masked()217 return pci_get_long(dev->msix_table + addr); in msix_table_mmio_read()257 return pci_get_long(dev->msix_pba + addr); in msix_pba_mmio_read()
189 serr_int = pci_get_long(shpc->config + SHPC_SERR_INT); in shpc_interrupt_update()754 dword_data = pci_get_long(d->shpc->config + d->shpc->cap in shpc_cap_write_config()
104 val |= (pcibus_t)pci_get_long(d->config + upper) << 32; in pci_config_get_pref_base()
1444 new_addr = pci_get_long(d->config + bar); in pci_config_get_bar_addr()1459 new_addr = pci_get_long(pf->config + bar); in pci_config_get_bar_addr()
475 pci_get_long(const uint8_t *config) in pci_get_long() function576 uint32_t val = pci_get_long(config); in pci_long_test_and_clear_mask()584 uint32_t val = pci_get_long(config); in pci_long_test_and_set_mask()631 uint32_t val = pci_get_long(config); in pci_set_long_by_mask()
489 uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); in ich9_lpc_pmbase_sci_update()490 uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL); in ich9_lpc_pmbase_sci_update()516 uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); in ich9_lpc_rcba_update()566 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); in ich9_lpc_config_write()591 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); in ich9_lpc_reset()
56 uint32_t pmbase = pci_get_long(s->dev.config + 0x48) & 0xff80UL; in pm_io_space_update()66 uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL; in smb_io_space_update()107 uint32_t v = pci_get_long(s->dev.config + 0x48); in pm_write_config()114 uint32_t v = pci_get_long(s->dev.config + 0x90); in pm_write_config()
34 pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND); in rp_write_config()
253 pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND); in cxl_rp_write_config()
329 base = pci_get_long(vdev->pdev.config + IGD_BDSM); in vfio_igd_quirk_data_write()402 return pci_get_long(vdev->pdev.config + offset); in vfio_igd_quirk_bdsm_read()
1868 tmp = PCI_EXT_CAP_NEXT(pci_get_long(config + tmp))) { in vfio_ext_cap_max_size()1892 pci_set_long(buf, (pci_get_long(buf) & ~mask) | val); in vfio_set_long_bits()1931 if (pci_get_long(pos) & (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | in vfio_pci_enable_rp_atomics()2110 uint32_t cap = pci_get_long(vdev->pdev.config + pos + PCI_EXP_DEVCAP); in vfio_check_pcie_flr()2248 ctrl = pci_get_long(vdev->pdev.config + pos + PCI_REBAR_CTRL); in vfio_setup_rebar_ecap()2255 ctrl = pci_get_long(vdev->pdev.config + pos + PCI_REBAR_CTRL + (i * 8)); in vfio_setup_rebar_ecap()2301 !pci_get_long(pdev->config + PCI_CONFIG_SPACE_SIZE)) { in vfio_add_ext_cap()2343 next = PCI_EXT_CAP_NEXT(pci_get_long(config + next))) { in vfio_add_ext_cap()2344 header = pci_get_long(config + next); in vfio_add_ext_cap()
54 uint32_t gcs = pci_get_long(lpc->chip_config + ICH9_CC_GCS); in tco_timer_expired()
860 cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]); in add_pci_device()
304 uint32_t data = pci_get_long(pbdev->pdev->config + in clp_service_call()
670 val = pci_get_long(buf); in virtio_address_space_write()