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/openbmc/linux/drivers/gpu/drm/ttm/tests/
H A Dttm_pool_test.c251 pt = &pool->caching[caching].orders[order]; in ttm_pool_alloc_order_caching_match()
280 pt_pool = &pool->caching[pool_caching].orders[order]; in ttm_pool_alloc_caching_mismatch()
281 pt_tt = &pool->caching[tt_caching].orders[order]; in ttm_pool_alloc_caching_mismatch()
314 pt_pool = &pool->caching[caching].orders[order]; in ttm_pool_alloc_order_mismatch()
315 pt_tt = &pool->caching[caching].orders[0]; in ttm_pool_alloc_order_mismatch()
355 pt = &pool->caching[caching].orders[order]; in ttm_pool_free_dma_alloc()
386 pt = &pool->caching[caching].orders[order]; in ttm_pool_free_no_dma_alloc()
406 pt = &pool->caching[caching].orders[order]; in ttm_pool_fini_basic()
H A Dttm_device_test.c179 pt = pool->caching[i].orders[j]; in ttm_device_init_pools()
/openbmc/linux/drivers/dma-buf/heaps/
H A Dsystem_heap.c54 static const unsigned int orders[] = {8, 4, 0}; variable
55 #define NUM_ORDERS ARRAY_SIZE(orders)
321 if (size < (PAGE_SIZE << orders[i])) in alloc_largest_available()
323 if (max_order < orders[i]) in alloc_largest_available()
326 page = alloc_pages(order_flags[i], orders[i]); in alloc_largest_available()
342 unsigned int max_order = orders[0]; in system_heap_allocate()
/openbmc/linux/drivers/gpu/drm/ttm/
H A Dttm_pool.c291 return &pool->caching[caching].orders[order]; in ttm_pool_select_type()
297 return &pool->caching[caching].orders[order]; in ttm_pool_select_type()
305 return &pool->caching[caching].orders[order]; in ttm_pool_select_type()
578 if (pt != &pool->caching[i].orders[j]) in ttm_pool_init()
604 if (pt != &pool->caching[i].orders[j]) in ttm_pool_fini()
740 ttm_pool_debugfs_orders(pool->caching[i].orders, m); in ttm_pool_debugfs()
/openbmc/linux/include/drm/ttm/
H A Dttm_pool.h77 struct ttm_pool_type orders[NR_PAGE_ORDERS]; member
/openbmc/phosphor-power/cold-redundancy/
H A Dcold_redundancy.cpp250 std::vector<uint8_t> orders = {}; in createPSU() local
253 orders.push_back(psu->order); in createPSU()
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-bayer.rst15 orders. See also `the Wikipedia article on Bayer filter
H A Dfield-order.rst80 If multiple field orders are possible the
81 driver must choose one of the possible field orders during
/openbmc/linux/tools/memory-model/Documentation/
H A Dglossary.txt29 a special operation that includes a load and which orders that
117 Fully Ordered: An operation such as smp_mb() that orders all of
120 that orders all of its CPU's prior accesses, itself, and
167 a special operation that includes a store and which orders that
H A Drecipes.txt232 The smp_store_release() macro orders any prior accesses against the
233 store, while the smp_load_acquire macro orders the load against any
273 smp_store_release(), but the rcu_dereference() macro orders the load only
310 The smp_wmb() macro orders prior stores against later stores, and the
311 smp_rmb() macro orders prior loads against later loads. Therefore, if
H A Dordering.txt11 1. Barriers (also known as "fences"). A barrier orders some or
67 First, the smp_mb() full memory barrier orders all of the CPU's prior
115 synchronize_srcu() and so on. However, these primitives have orders
/openbmc/linux/Documentation/
H A Datomic_t.txt194 smp_mb__before_atomic() orders all earlier accesses against the RMW op
195 itself and all accesses following it, and smp_mb__after_atomic() orders all
226 a RELEASE because it orders preceding instructions against both the read
/openbmc/qemu/target/arm/tcg/
H A Dvfp-uncond.decode31 # and a one-bit field which are assembled in different orders
H A Dvfp.decode31 # and a one-bit field which are assembled in different orders
/openbmc/qemu/target/ppc/translate/
H A Dmisc-impl.c.inc107 * It separately also orders memory for operations in the set:
/openbmc/openbmc/poky/meta/files/common-licenses/
H A DSGI-B-1.158 …orders applicable to dispositions of Covered Code, including without limitation export, re-export,…
H A DIntel98 compliance with all laws, regulations, orders, or other restrictions of the
H A DSGI-B-1.056 …orders, in connection with any and all dispositions of Covered Code, including but not limited to,…
H A DIntel-ACPI34 …t/re-export of the software is in compliance with all laws, regulations, orders, or other restrict…
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-synology-ds116.dts53 * and takes single-character orders :
/openbmc/qemu/docs/devel/
H A Dsecure-coding-practices.rst73 The guest may access device registers in unusual orders or at unexpected
/openbmc/linux/tools/virtio/virtio-trace/
H A DREADME9 - controlled by start/stop orders from a Host
/openbmc/linux/tools/memory-model/
H A Dlock.cat8 * Generate coherence orders and handle lock operations
/openbmc/linux/Documentation/core-api/
H A Dgenalloc.rst49 that state, so one of the first orders of business is usually to add memory
/openbmc/docs/designs/
H A Dboot-progress.md97 support them in different orders. This document does not try to set any

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