Home
last modified time | relevance | path

Searched refs:operands (Results 1 – 25 of 33) sorted by relevance

12

/openbmc/qemu/target/xtensa/
H A Dxtensa-isa-internal.h106 xtensa_arg_internal *operands; /* Array[num_operands]. */ member
184 xtensa_operand_internal *operands; member
H A Dxtensa-isa.c846 operand_id = iclass->operands[opnd].u.operand_id; in get_operand()
847 return &intisa->operands[operand_id]; in get_operand()
877 if (iclass->operands[opnd].inout == 's') { in xtensa_operand_is_visible()
881 operand_id = iclass->operands[opnd].u.operand_id; in xtensa_operand_is_visible()
882 intop = &intisa->operands[operand_id]; in xtensa_operand_is_visible()
902 inout = iclass->operands[opnd].inout; in xtensa_operand_inout()
/openbmc/qemu/scripts/qapi/
H A Dcommon.py221 def gen_infix(operator: str, operands: Sequence[Any]) -> str:
222 return operator.join([do_gen(o, True) for o in operands])
/openbmc/openbmc/poky/meta/recipes-support/mpfr/
H A Dmpfr_4.2.2.bb2 …d semantics: the functions are completely specified on all the possible operands and the results d…
/openbmc/u-boot/include/bedbug/
H A Dppc.h387 extern struct operand operands[];
H A Dtables.h14 struct operand operands[] = { variable
54 const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]);
/openbmc/u-boot/common/
H A Dbedbug.c251 opr = &operands[ctx->op->fields[field] - 1]; in print_operands()
392 opr = &operands[op->fields[i] - 1]; in get_operand_value()
801 oper[n_operands] = &operands[opc->fields[n_operands] - 1]; in asmppc()
/openbmc/qemu/docs/devel/
H A Dtcg-ops.rst51 variable operands, input variable operands and constant operands.
56 In the textual form, output operands usually come first, followed by
57 input operands, followed by constant operands. The output type is
972 version. Aliases are specified in the input operands as for GCC.
H A Ddecodetree.rst108 pattern and the ``OR`` pattern put their operands into the same named
/openbmc/u-boot/doc/
H A DREADME.POST442 different combinations of operands, read the condition register
446 the operands, the condition field to save the result in and the
456 operands, expected results and expected states of the condition
460 iteration r0/r1 will be used as operands and r2 for result. On
461 the second iteration, r1/r2 will be used as operands and r3 as
/openbmc/openbmc/poky/meta/recipes-bsp/v86d/v86d/
H A DUpdate-x86emu-from-X.org.patch1310 modrm byte, for byte operands. Also enables the decoding of instructions.
1378 modrm byte, for word operands. Also enables the decoding of instructions.
1444 modrm byte, for dword operands. Also enables the decoding of instructions.
1508 modrm byte, for word operands, modified from above for the weirdo
1509 special case of segreg operands. Also enables the decoding of instructions.
14851 - register u32 res; /* all operands in native machine order */
14853 + register u32 res; /* all operands in native machine order */
14894 - register u32 res; /* all operands in native machine order */
14896 + register u32 res; /* all operands in native machine order */
14937 - register u32 lo; /* all operands in native machine order */
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dneon-dp.decode93 # assembly the operands are listed "backwards", ie in the order
97 # function code. We would otherwise need to manually swap the operands
H A Dmve.decode86 # assembly the operands are listed "backwards", ie in the order
H A Dsve.decode175 # Two register operands with a 6-bit signed immediate.
/openbmc/qemu/target/hexagon/
H A DREADME65 By convention, the operands are identified by letter
245 VLIW packet semantics differ from serial semantics in that all input operands
/openbmc/qemu/disas/
H A Dalpha.c53 unsigned char operands[4]; member
1839 for (opindex = opcode->operands; *opindex != 0; opindex++) in print_insn_alpha()
1860 if (opcode->operands[0] != 0) in print_insn_alpha()
1865 for (opindex = opcode->operands; *opindex != 0; opindex++) in print_insn_alpha()
/openbmc/qemu/fpu/
H A Dsoftfloat-parts.c.inc1516 * If both operands are NaNs, a QNaN is returned.
1519 * but unless both operands are NaNs,
1583 /* For two negative operands, invert the magnitude comparison. */
/openbmc/qemu/target/i386/tcg/
H A Ddecode-new.c.inc46 * For memory-only operands, if the emitter functions wants to rely on
62 * Vector operands
82 * for 256-bit AVX operands, etc. It is used for conversion operations
209 * clearer to write all three operands explicitly, because the
871 * from the first two operands due to the V operand picking higher entries of
908 * There are some mistakes in the operands in the manual, and the load/store/register
918 * operands, which must therefore be dq; MOVLPD and MOVLPS also write the high
2240 /* First compute size of operands in order to initialize s->rip_offset. */
H A Demit.c.inc230 /* MOST legacy SSE instructions require aligned memory operands, but not all. */
1116 * There are two output operands, so zero OP1's high 128 bits
3407 * RCx operations are invariant modulo 8*operand_size+1. For 8 and 16-bit operands,
/openbmc/qemu/target/mips/tcg/
H A Dnanomips_translate.c.inc1118 /* Load needed operands */
1369 /* operands of same sign, result different sign */
2295 /* Load needed operands and calculate btarget */
2420 /* Load needed operands and calculate btarget */
/openbmc/qemu/target/xtensa/core-lx106/
H A Dxtensa-modules.c.inc1272 /* Instruction operands. */
1976 static xtensa_operand_internal operands[] = {
7659 65, operands,
/openbmc/qemu/target/xtensa/core-fsf/
H A Dxtensa-modules.c.inc1296 /* Instruction operands. */
2066 static xtensa_operand_internal operands[] = {
9816 70, operands,
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dxtensa-modules.c.inc1496 /* Instruction operands. */
2418 static xtensa_operand_internal operands[] = {
11357 77, operands,
/openbmc/qemu/tcg/s390x/
H A Dtcg-target.c.inc1417 /* Swap operands so that we can use LEU/GTU/GT/LE. */
3712 * Facility 45 is a big bin that contains: distinct-operands,
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dxtensa-modules.c.inc1735 /* Instruction operands. */
2681 static xtensa_operand_internal operands[] = {
15196 93, operands,

12