Revision tags: v9.2.0, v9.1.2, v9.1.1, v9.1.0 |
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28188253 |
| 06-May-2024 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-hex-20240505' of https://github.com/quic/qemu into staging
Short-circuit for packets with r/w and no overlap
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEPWaq5HRZSCTIjOD4GlSv
Merge tag 'pull-hex-20240505' of https://github.com/quic/qemu into staging
Short-circuit for packets with r/w and no overlap
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEPWaq5HRZSCTIjOD4GlSvuOVkbDIFAmY4FR8ACgkQGlSvuOVk # bDLEfxAAup6v9J4n2/q88FXfLGgx1EfZrT01gOM/48mwngNNQJGJQySe2GLl0G8S # 1hx/Ym3jbikic8HL80v8FyCr4gNRshEY7xKpCfvY9lsgnCRbhEvoV/hZqucmLQAt # 1SIhFSsi5h8gyZDTvXhH75v3qGvYjQ7fQBhy2JbRsPjthdHBh9xi6Na60wlqfNZq # oGsVtY7sv1uHsvDKBi3JoXWckSK99R38BHY6zPoStarRZACkkLdX6KHxeX88TUt1 # whIUYUS/K0nRVxzekdq/+m8UJYrXnW/0cliM5mLFHDGlsV+qjdcIRrfaPWBO0eFN # kXeZU2BWLCdP2M52FHI4FllnIRpX5OGkxjR6x8Pc9r+EGciwGRU7xeAlqBxKQSZP # e3oXtV6oKxg69xBgHE5HcKbt6bX5EZR/sUcbAoGA41UssaiMyj3wbg1cy2UxXu2J # 7oJyywJUggWGSoCIIJJ95YgpUrIg73Yg6pOjfhKW1w/V2SuQPGG0XTXrwe7J6uGi # VAqyu55p2oiW8Gk4Lvl1SfWgxkVeZa/NcxTmXNEWFnT7vatqwez0O5pxIkxdSCFE # lRv7PuFT5nhQ/gg12zGqqRiOrMOMQitHFzJ9sUNu7J4Y7W5R4gzRW19ucojLt0lH # fT83Ra+Eex1Cu3DsuvWkokxFikxXP1Ll297Jr1JhOPewTtvlxvI= # =Q8/k # -----END PGP SIGNATURE----- # gpg: Signature made Sun 05 May 2024 04:24:15 PM PDT # gpg: using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32 # gpg: Good signature from "Brian Cain (QUIC) <quic_bcain@quicinc.com>" [unknown] # gpg: aka "Brian Cain <bcain@kernel.org>" [unknown] # gpg: aka "Brian Cain (QuIC) <bcain@quicinc.com>" [unknown] # gpg: aka "Brian Cain (CAF) <bcain@codeaurora.org>" [unknown] # gpg: aka "bcain" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6350 20F9 67A7 7164 79EF 49E0 175C 464E 541B 6D47 # Subkey fingerprint: 3D66 AAE4 7459 4824 C88C E0F8 1A54 AFB8 E564 6C32
* tag 'pull-hex-20240505' of https://github.com/quic/qemu: Hexagon (target/hexagon) Remove hex_common.read_attribs_file Hexagon (target/hexagon) Remove gen_shortcode.py Hexagon (target/hexagon) Remove gen_op_regs.py Hexagon (target/hexagon) Remove uses of op_regs_generated.h.inc Hexagon (tests/tcg/hexagon) Test HVX .new read from high half of pair Hexagon (target/hexagon) Mark has_pred_dest in trans functions Hexagon (target/hexagon) Mark dest_idx in trans functions Hexagon (target/hexagon) Mark new_read_idx in trans functions Hexagon (target/hexagon) Add is_old/is_new to Register class Hexagon (target/hexagon) Only pass env to generated helper when needed Hexagon (target/hexagon) Pass SP explicitly to helpers that need it Hexagon (target/hexagon) Pass P0 explicitly to helpers that need it Hexagon (target/hexagon) Enable more short-circuit packets (HVX) Hexagon (target/hexagon) Enable more short-circuit packets (scalar core) Hexagon (target/hexagon) Analyze reads before writes
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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582c59ef |
| 06-Mar-2024 |
Taylor Simpson <ltaylorsimpson@gmail.com> |
Hexagon (target/hexagon) Remove gen_shortcode.py
This data structure is not used
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Reviewed-by: Ph
Hexagon (target/hexagon) Remove gen_shortcode.py
This data structure is not used
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240307032327.4799-9-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
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b45c1b51 |
| 06-Mar-2024 |
Taylor Simpson <ltaylorsimpson@gmail.com> |
Hexagon (target/hexagon) Remove gen_op_regs.py
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-8-ltaylorsimpson@
Hexagon (target/hexagon) Remove gen_op_regs.py
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240307032327.4799-8-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
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76eaa971 |
| 01-Feb-2024 |
Taylor Simpson <ltaylorsimpson@gmail.com> |
Hexagon (target/hexagon) Analyze reads before writes
We divide gen_analyze_funcs.py into 3 phases Declare the operands Analyze the register reads Analyze the register writes
We also cre
Hexagon (target/hexagon) Analyze reads before writes
We divide gen_analyze_funcs.py into 3 phases Declare the operands Analyze the register reads Analyze the register writes
We also create special versions of ctx_log_*_read for new operands Check that the operand is written before the read
This is a precursor to improving the analysis for short-circuiting the packet semantics in a subsequent commit
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240201103340.119081-2-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
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4a4efae4 |
| 23-Jan-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-hex-20240121' of https://github.com/quic/qemu into staging
Coverity fix, cross toolchain update, switch to decodetree
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEPWaq5HRZSCT
Merge tag 'pull-hex-20240121' of https://github.com/quic/qemu into staging
Coverity fix, cross toolchain update, switch to decodetree
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEPWaq5HRZSCTIjOD4GlSvuOVkbDIFAmWuBTwACgkQGlSvuOVk # bDKP2xAAoRj18rgFPSXu1Dmh34uhZ2uxTAdqyozLqlHJBBiaUxA7EyZJqvOc+8Ti # owLIF5fYPL1MZ7EfwW8FZjAc29WtGzmRY/ZwEDZVgdVAyLCnZ0fF785caWdxH5L2 # bA2i9hNfCJvd3HqfeJ0JXgWD/rF5OjlSKWwYOGPkfjkDnSwAV9LlxGq+yhxjpYcc # uSwVUbIipzUQoH5O53xXt2OUSW+WNUYzKpsnLjW/2wTBgXpBXIuxUzao/Iv37hdo # OMcDiM7mH6ic5JoiNyL9pmquOCpwTGHWyREaiWga1IzJIbRKn/Ypr0N1KsTAc28V # 10GcbMpwKHG/umzhi9BoiPTfD1jXIzYWasH+RyBMz3bNCCaKuJmGSnohbud8UVDH # GJHhF72RhBt/bYnwmoYW3OXvk8X+mL7vuq4lKDAB2XNDjAS3+mcGuSu4KJDJeXi9 # l5/Kx0Aef0mmzEbXALErpYP6TTlgj2CCsym3SXi0UuAI94v1sV346jejebMRUndq # UKKUXb+oC0BUNBUPdnaUIr5GAnQl5Xm2E3pihl28NO+U0xvHQSSxInv84Y3JGDiW # /ui4ZYux0V+iHok9MO0ugaIF9Z1o16D43TkZdLbulm8ODuCEz8CuQjDVoayWj3CV # wb290m96zgS03aRAM+yQa+irTrOJ5bh1XOP1dr/FGQHln0mUCCQ= # =aIh2 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 22 Jan 2024 06:03:40 GMT # gpg: using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32 # gpg: Good signature from "Brian Cain <bcain@kernel.org>" [full] # gpg: aka "Brian Cain (QuIC) <bcain@quicinc.com>" [full] # gpg: aka "Brian Cain (CAF) <bcain@codeaurora.org>" [full] # gpg: aka "bcain" [full] # Primary key fingerprint: 6350 20F9 67A7 7164 79EF 49E0 175C 464E 541B 6D47 # Subkey fingerprint: 3D66 AAE4 7459 4824 C88C E0F8 1A54 AFB8 E564 6C32
* tag 'pull-hex-20240121' of https://github.com/quic/qemu: target/hexagon: reduce scope of def_regnum, remove dead assignment Hexagon (target/hexagon) Remove old dectree.py Hexagon (target/hexagon) Use QEMU decodetree (16-bit instructions) Hexagon (target/hexagon) Use QEMU decodetree (32-bit instructions) Hexagon (target/hexagon) Remove dead functions from hex_common.py Hexagon (target/hexagon) Remove unused WRITES_PRED_REG attribute Hexagon (target/hexagon) Make generators object oriented - gen_analyze_funcs Hexagon (target/hexagon) Make generators object oriented - gen_op_regs Hexagon (target/hexagon) Make generators object oriented - gen_idef_parser_funcs Hexagon (target/hexagon) Make generators object oriented - gen_helper_funcs Hexagon (target/hexagon) Make generators object oriented - gen_helper_protos Hexagon (target/hexagon) Make generators object oriented - gen_tcg_funcs Hexagon (target/hexagon) Clean up handling of modifier registers Hexagon (target/hexagon) Fix shadow variable when idef-parser is off tests/docker: Hexagon toolchain update
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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f6c01009 |
| 15-Jan-2024 |
Taylor Simpson <ltaylorsimpson@gmail.com> |
Hexagon (target/hexagon) Use QEMU decodetree (16-bit instructions)
Section 10.3 of the Hexagon V73 Programmer's Reference Manual
A duplex is encoded as a 32-bit instruction with bits [15:14] set to
Hexagon (target/hexagon) Use QEMU decodetree (16-bit instructions)
Section 10.3 of the Hexagon V73 Programmer's Reference Manual
A duplex is encoded as a 32-bit instruction with bits [15:14] set to 00. The sub-instructions that comprise a duplex are encoded as 13-bit fields in the duplex.
Create a decoder for each subinstruction class (a, l1, l2, s1, s2).
Extend gen_trans_funcs.py to handle all instructions rather than filter by instruction class.
There is a g_assert_not_reached() in decode_insns() in decode.c to verify we never try to use the old decoder on 16-bit instructions.
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240115221443.365287-3-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
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1547a2d3 |
| 15-Jan-2024 |
Taylor Simpson <ltaylorsimpson@gmail.com> |
Hexagon (target/hexagon) Use QEMU decodetree (32-bit instructions)
The Decodetree Specification can be found here https://www.qemu.org/docs/master/devel/decodetree.html
Covers all 32-bit instructio
Hexagon (target/hexagon) Use QEMU decodetree (32-bit instructions)
The Decodetree Specification can be found here https://www.qemu.org/docs/master/devel/decodetree.html
Covers all 32-bit instructions, including HVX
We generate separate decoders for each instruction class. The reason will be more apparent in the next patch in this series.
We add 2 new scripts gen_decodetree.py Generate the input to decodetree.py gen_trans_funcs.py Generate the trans_* functions used by the output of decodetree.py
Since the functions generated by decodetree.py take DisasContext * as an argument, we add the argument to a couple of functions that didn't need it previously. We also set the insn field in DisasContext during decode because it is used by the trans_* functions.
There is a g_assert_not_reached() in decode_insns() in decode.c to verify we never try to use the old decoder on 32-bit instructions
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240115221443.365287-2-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
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800af0aa |
| 05-Oct-2023 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-tcg-20231004' of https://gitlab.com/rth7680/qemu into staging
accel: Introduce AccelClass::cpu_common_[un]realize accel: Target agnostic code movement accel/tcg: Cleanups to use CPUS
Merge tag 'pull-tcg-20231004' of https://gitlab.com/rth7680/qemu into staging
accel: Introduce AccelClass::cpu_common_[un]realize accel: Target agnostic code movement accel/tcg: Cleanups to use CPUState instead of CPUArchState accel/tcg: Move CPUNegativeOffsetState into CPUState tcg: Split out tcg init functions to tcg/startup.h linux-user/hppa: Fix struct target_sigcontext layout build: Remove --enable-gprof
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmUdsL4dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/iYggAvDJEyMCAXSSH97BA # wZT/2D/MFIhOMk6xrQRnrXfrG70N0iVKz44jl9j7k1D+9BOHcso//DDJH3c96k9A # MgDb6W2bsWvC15/Qw6BALf5bb/II0MJuCcQvj3CNX5lNkXAWhwIOBhsZx7V9ST1+ # rihN4nowpRWdV5GeCjDGaJW455Y1gc96hICYHy6Eqw1cUgUFt9vm5aYU3FHlat29 # sYRaVYKUL2hRUPPNcPiPq0AaJ8wN6/s8gT+V1UvTzkhHqskoM4ZU89RchuXVoq1h # SvhKElyULMRzM7thWtpW8qYJPj4mxZsKArESvHjsunGD6KEz3Fh1sy6EKRcdmpG/ # II1vkg== # =k2Io # -----END PGP SIGNATURE----- # gpg: Signature made Wed 04 Oct 2023 14:36:46 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20231004' of https://gitlab.com/rth7680/qemu: (47 commits) tcg/loongarch64: Fix buid error tests/avocado: Re-enable MIPS Malta tests (GitLab issue #1884 fixed) build: Remove --enable-gprof linux-user/hppa: Fix struct target_sigcontext layout tcg: Split out tcg init functions to tcg/startup.h tcg: Remove argument to tcg_prologue_init accel/tcg: Make cpu-exec-common.c a target agnostic unit accel/tcg: Make icount.o a target agnostic unit accel/tcg: Make monitor.c a target-agnostic unit accel/tcg: Rename target-specific 'internal.h' -> 'internal-target.h' exec: Rename target specific page-vary.c -> page-vary-target.c exec: Rename cpu.c -> cpu-target.c accel: Rename accel-common.c -> accel-target.c accel: Make accel-blocker.o target agnostic accel/tcg: Restrict dump_exec_info() declaration exec: Move cpu_loop_foo() target agnostic functions to 'cpu-common.h' exec: Make EXCP_FOO definitions target agnostic accel/tcg: move ld/st helpers to ldst_common.c.inc accel/tcg: Unify user and softmmu do_[st|ld]*_mmu() accel/tcg: Remove env_tlb() ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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ad75a51e |
| 13-Sep-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Rename cpu_env to tcg_env
Allow the name 'cpu_env' to be used for something else.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@li
tcg: Rename cpu_env to tcg_env
Allow the name 'cpu_env' to be used for something else.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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c5ea91da |
| 08-Sep-2023 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging
trivial patches for 2023-09-08
# -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEe3O61ovnosKJMUsicBtPaxppPlkFAmT68tM
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging
trivial patches for 2023-09-08
# -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEe3O61ovnosKJMUsicBtPaxppPlkFAmT68tMPHG1qdEB0bHMu # bXNrLnJ1AAoJEHAbT2saaT5ZbEwH/2XcX1f4KcEJbgUn0JVhGQ5GH2c2jepZlkTZ # 2dhvdEECbOPMg73hty0fyyWlyuLWdJ9cMpONfMtzmHTH8RKEOAbpn/zusyo3H+48 # 6cunyUpBqbmb7MHPchrN+JmvtvaSPSazsj2Zdkh+Y4WlfEYj+yVysQ4zQlBlRyHv # iOTi6OdjxXg1QcbtJxAUhp+tKaRJzagiCpLkoyW2m8DIuV9cLVHMJsE3OMgfKNgK # /S+O1fLcaDhuSCrHAbZzArF3Tr4bfLqSwDtGCJfQpqKeIQDJuI+41GLIlm1nYY70 # IFJzEWMOrX/rcMG1CQnUFZOOyDSO+NfILwNnU+eyM49MUekmY54= # =mmPS # -----END PGP SIGNATURE----- # gpg: Signature made Fri 08 Sep 2023 06:09:23 EDT # gpg: using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59 # gpg: issuer "mjt@tls.msk.ru" # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [full] # gpg: aka "Michael Tokarev <mjt@debian.org>" [full] # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59
* tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: (22 commits) qxl: don't assert() if device isn't yet initialized hw/net/vmxnet3: Fix guest-triggerable assert() tests/qtest/usb-hcd: Remove the empty "init" tests target/ppc: use g_free() in test_opcode_table() hw/ppc: use g_free() in spapr_tce_table_post_load() trivial: Simplify the spots that use TARGET_BIG_ENDIAN as a numeric value accel/tcg: Fix typo in translator_io_start() description tests/qtest/test-hmp: Fix migrate_set_parameter xbzrle-cache-size test docs tests: Fix use of migrate_set_parameter qemu-options.hx: Rephrase the descriptions of the -hd* and -cdrom options hw/display/xlnx_dp: update comments block: spelling fixes misc/other: spelling fixes qga/: spelling fixes tests/: spelling fixes scripts/: spelling fixes include/: spelling fixes audio: spelling fixes xen: spelling fix riscv: spelling fixes ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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6c67d98c |
| 14-Jul-2023 |
Michael Tokarev <mjt@tls.msk.ru> |
hexagon: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Brian Cain <bcain@quicinc.com>
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449d6d9e |
| 18-May-2023 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-hex-20230518-1' of https://github.com/quic/qemu into staging
Hexagon update
# -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmRmgQgACgkQewJE+xLe # RC
Merge tag 'pull-hex-20230518-1' of https://github.com/quic/qemu into staging
Hexagon update
# -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmRmgQgACgkQewJE+xLe # RCJLtAf8C/0kQRa4mjnbsztXuFyca53UxAv3BSBEDla4ZcMfFBoVJsGB3OP7IPXd # KBQpkLyJAVye9idex5xqdp9nIfoGKDTsc6YtCfGujZ17cDpzLRDpHdUTex8PcZYK # wpfM3hoVJsYRBMsojZ4OaxatjFQ+FWzrIH6FcgH086Q8TH4w9dZLNEJzHC4lOj0s # 7qOuw2tgm+vOVlzsk/fv6/YD/BTeZTON3jgTPvAnvdRLb/482UpM9JkJ8E4rbte3 # Ss5PUK8QTQHU0yamspGy/PfsYxiptM+jIWGd836fAGzwF12Ug27mSc1enndRtQVW # pQTdnOnWuuRzOwEpd7x3xh9upACm4g== # =1CyJ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 18 May 2023 12:48:24 PM PDT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422
* tag 'pull-hex-20230518-1' of https://github.com/quic/qemu: (44 commits) Hexagon (linux-user/hexagon): handle breakpoints Hexagon (gdbstub): add HVX support Hexagon (gdbstub): fix p3:0 read and write via stub Hexagon: add core gdbstub xml data for LLDB gdbstub: add test for untimely stop-reply packets gdbstub: only send stop-reply packets when allowed to Remove test_vshuff from hvx_misc tests Hexagon (decode): look for pkts with multiple insns at the same slot Hexagon (iclass): update J4_hintjumpr slot constraints Hexagon: append eflags to unknown cpu model string Hexagon: list available CPUs with `-cpu help` Hexagon (target/hexagon/*.py): raise exception on reg parsing error target/hexagon: fix = vs. == mishap Hexagon (target/hexagon) Additional instructions handled by idef-parser Hexagon (target/hexagon) Move items to DisasContext Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext Hexagon (target/hexagon) Move pred_written to DisasContext Hexagon (target/hexagon) Move new_pred_value to DisasContext Hexagon (target/hexagon) Move new_value to DisasContext Hexagon (target/hexagon) Make special new_value for USR ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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0fc56c43 |
| 27-Apr-2023 |
Taylor Simpson <tsimpson@quicinc.com> |
Hexagon (target/hexagon) Move items to DisasContext
The following items in the CPUHexagonState are only used for bookkeeping within the translation of a packet. With recent changes that eliminate t
Hexagon (target/hexagon) Move items to DisasContext
The following items in the CPUHexagonState are only used for bookkeeping within the translation of a packet. With recent changes that eliminate the need to free TCGv variables, these make more sense to be transient and kept in DisasContext.
The following items are moved dczero_addr branch_taken this_PC
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-22-tsimpson@quicinc.com>
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6aa4f1d1 |
| 27-Apr-2023 |
Taylor Simpson <tsimpson@quicinc.com> |
Hexagon (target/hexagon) Make special new_value for USR
Precursor to moving new_value from the global state to DisasContext
USR will need to stay in the global state because some helpers will set i
Hexagon (target/hexagon) Make special new_value for USR
Precursor to moving new_value from the global state to DisasContext
USR will need to stay in the global state because some helpers will set it's value
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-17-tsimpson@quicinc.com>
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07540a28 |
| 27-Apr-2023 |
Taylor Simpson <tsimpson@quicinc.com> |
Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_write
Add DisasContext arg to gen_log_reg_write_pair also
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Hend
Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_write
Add DisasContext arg to gen_log_reg_write_pair also
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-3-tsimpson@quicinc.com>
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#
fc2622f6 |
| 27-Apr-2023 |
Taylor Simpson <tsimpson@quicinc.com> |
Hexagon (target/hexagon) Add support for v68/v69/v71/v73
Add support for the ELF flags Move target/hexagon/cpu.[ch] to be v73 Change the compiler flag used by "make check-tcg"
The decbin instructio
Hexagon (target/hexagon) Add support for v68/v69/v71/v73
Add support for the ELF flags Move target/hexagon/cpu.[ch] to be v73 Change the compiler flag used by "make check-tcg"
The decbin instruction is removed in Hexagon v73, so check the version before trying to compile the instruction.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-2-tsimpson@quicinc.com>
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Revision tags: v8.0.0 |
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#
aa4af821 |
| 10-Mar-2023 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-hex-20230306' of https://github.com/quic/qemu into staging
Hexagon (target/hexagon) update
# -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmQGzGYACg
Merge tag 'pull-hex-20230306' of https://github.com/quic/qemu into staging
Hexagon (target/hexagon) update
# -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmQGzGYACgkQewJE+xLe # RCJfxggAgAY9fqUxKk5FxziMX6sVxx2SiYGU1biABtHyduQvJ43U7In4cnbC65FL # Pn+ZSixPRh51Ij2s9FTzDQ8IUNt/k1W7gCoEC3I0wDbQHdICEIlx30ry68QlUgOa # T6ZDquJkanwFjb7kMnyM4LRBBxLG+OuYvKe1e+nzun0LDlfTS/sHitRlf4AJEBOK # 9h/Bdy81RcWlLzlc5tmD0f9rhtmkkFCTu/TGLt4G6sfn1xZbRdh5N1cFfUShPlQM # qAgj+JgBOQoPKaBhQZnA3Ps9ZEM4+/8KPsr5oGweAcjqD8+kMGCmi2jv+60ES5Uq # EDpn25COw7BVAo6vP/JfBEiZTg+YpA== # =FDSG # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Mar 2023 05:32:22 GMT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422
* tag 'pull-hex-20230306' of https://github.com/quic/qemu: Hexagon (target/hexagon) Improve code gen for predicated HVX instructions Hexagon (target/hexagon) Reduce manipulation of slot_cancelled Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair] Hexagon (target/hexagon) Change subtract from zero to change sign Hexagon (tests/tcg/hexagon) Enable HVX tests Hexagon (tests/tcg/hexagon) Remove __builtin from scatter_gather Hexagon (tests/tcg/hexagon) Update preg_alias.c Hexagon (target/hexagon) Analyze packet for HVX Hexagon (target/hexagon) Don't set pkt_has_store_s1 when not needed Hexagon (target/hexagon) Analyze packet before generating TCG Hexagon (target/hexagon) Add overrides for dealloc-return instructions Hexagon (target/hexagon) Add overrides for endloop1/endloop01 Hexagon (target/hexagon) Add overrides for callr Hexagon (target/hexagon) Add overrides for jumpr31 instructions target/hexagon/idef-parser: Remove unused code paths target/hexagon/idef-parser: Elide mov in gen_pred_assign Hexagon (target/hexagon) Restore --disable-hexagon-idef-parser build
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
c2b33d0b |
| 06-Mar-2023 |
Taylor Simpson <tsimpson@quicinc.com> |
Hexagon (target/hexagon) Improve code gen for predicated HVX instructions
The following improvements are made for predicated HVX instructions During gen_commit_hvx, unconditionally move the "new
Hexagon (target/hexagon) Improve code gen for predicated HVX instructions
The following improvements are made for predicated HVX instructions During gen_commit_hvx, unconditionally move the "new" value into the dest Don't set slot_cancelled Remove runtime bookkeeping of which registers were updated Reduce the cases where gen_log_vreg_write[_pair] is called It's only needed for special operands VxxV and VyV Remove gen_log_qreg_write
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230307025828.1612809-15-tsimpson@quicinc.com>
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#
10849c26 |
| 06-Mar-2023 |
Taylor Simpson <tsimpson@quicinc.com> |
Hexagon (target/hexagon) Analyze packet before generating TCG
We create a new generator that creates an analyze_<tag> function for each instruction. Currently, these functions record the writes to
Hexagon (target/hexagon) Analyze packet before generating TCG
We create a new generator that creates an analyze_<tag> function for each instruction. Currently, these functions record the writes to R, P, and C registers by calling ctx_log_reg_write[_pair] or ctx_log_pred_write.
During gen_start_packet, we invoke the analyze_<tag> function for each instruction in the packet, and we mark the implicit register and predicate writes.
Doing the analysis up front has several advantages - We remove calls to ctx_log_* from gen_tcg_funcs.py and genptr.c - After the analysis is performed, we can initialize hex_new_value for each of the predicated assignments rather than during TCG generation for the instructions - This is a stepping stone for future work where the analysis will include the set of registers that are read. In cases where the packet doesn't have an overlap between the registers that are written and registers that are read, we can avoid the intermediate step of writing to hex_new_value. Note that other checks will also be needed (e.g., no instructions can raise an exception).
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230307025828.1612809-6-tsimpson@quicinc.com>
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#
f003dd8d |
| 06-Mar-2023 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging
tcg: Merge two sequential labels accel/tcg: Retain prot flags from tlb_fill accel/tcg: Honor TLB_DISCARD_WRITE in atomic
Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging
tcg: Merge two sequential labels accel/tcg: Retain prot flags from tlb_fill accel/tcg: Honor TLB_DISCARD_WRITE in atomic_mmu_lookup accel/tcg: Honor TLB_WATCHPOINTS in atomic_mmu_lookup target/sparc: Use tlb_set_page_full include/qemu/cpuid: Introduce xgetbv_low tcg/i386: Mark Win64 call-saved vector regs as reserved tcg: Decode the operand to INDEX_op_mb in dumps
Portion of the target/ patchset which eliminates use of tcg_temp_free* Portion of the target/ patchset which eliminates use of tcg_const*
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmQFNegdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9WsQf+Ljs3WA5lvMPlpaSn # Li35ay/A1f2cU6FYspl81su4/c7Ft9Q8rkPF4K1n1rwuvqR91G25WTQIrw8NFPXZ # VU9GNGQc1qIVYO/hAH3fvgDmPxUF+tJDgT/BTNc1ldy6/v7QM3GWcEy8+O3H9S+K # uj6vIuWke0ukq6ZGmSAZnXEaJFq3HU26mcP4KxDxfIUcezMtDVp6QevqzVxM65aa # pUDh3qtsLGOxIYwthvu6avMQXORBhSB75awCuYH4QPJRpr3ahigcGsCr2gdVAQ8p # R7BbpUUdK5Huos971oouJrt5FwwbVgGEx78eF27sl0H8QMoNhsfyn6PcN8nPENLJ # MZYd+w== # =8goQ # -----END PGP SIGNATURE----- # gpg: Signature made Mon 06 Mar 2023 00:38:00 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu: (84 commits) target/xtensa: Avoid tcg_const_i32 target/xtensa: Split constant in bit shift target/xtensa: Use tcg_gen_subfi_i32 in translate_sll target/xtensa: Avoid tcg_const_i32 in translate_l32r target/xtensa: Tidy translate_clamps target/xtensa: Tidy translate_bb target/sparc: Avoid tcg_const_{tl,i32} target/s390x: Split out gen_ri2 target/riscv: Avoid tcg_const_* target/microblaze: Avoid tcg_const_* throughout target/i386: Simplify POPF target/hexagon/idef-parser: Use gen_constant for gen_extend_tcg_width_op target/hexagon/idef-parser: Use gen_tmp for gen_rvalue_pred target/hexagon/idef-parser: Use gen_tmp for gen_pred_assign target/hexagon/idef-parser: Use gen_tmp for LPCFG target/hexagon: Use tcg_constant_* for gen_constant_from_imm docs/devel/tcg-ops: Drop recommendation to free temps tracing: remove transform.py include/exec/gen-icount: Drop tcg_temp_free in gen_tb_start target/tricore: Drop tcg_temp_free ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
09538b08 |
| 24-Feb-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hexagon: Drop tcg_temp_free from C code
Translators are no longer required to free tcg temporaries.
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richa
target/hexagon: Drop tcg_temp_free from C code
Translators are no longer required to free tcg temporaries.
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
a2b5f8b8 |
| 01-Mar-2023 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-tcg-20230301' of https://gitlab.com/rth7680/qemu into staging
helper-head: Add fpu/softfloat-types.h softmmu: Use memmove in flatview_write_continue tcg: Add sign param to probe_acce
Merge tag 'pull-tcg-20230301' of https://gitlab.com/rth7680/qemu into staging
helper-head: Add fpu/softfloat-types.h softmmu: Use memmove in flatview_write_continue tcg: Add sign param to probe_access_flags, probe_access_full tcg: Convert TARGET_TB_PCREL to CF_PCREL tcg: Simplify temporary lifetimes for translators
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmP/jWUdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9TcQf7B7+K/lrWvUVhZ4By # 7zrNIJKGwsxuQhGq9mS2Nx9ds9es5mS8SQT1ieNG6a51n6Gq8S2B8yFCRFdlDZWD # /QrMSjxrs+4c6pNHZu4v20Huy/VW0y004eYdGc8Lu5cXTDpy1mUZ2PrZYlWNQEVY # 4Ts5rTWdSZHRU1+dbB8MTWlml9//++TPB+ZvzqSb8jnRJfw4z7ijVJjUEEb93gQg # 8S3JiPU6d1ZzoXzGMK7Wd0MMi4pQUZkaX1HOpzvmQXjeErSP87CZvvji/Cucm8iW # rJ4U7t99nmZDqG9W1zdZfYfKNp4nLlfVldQWFVIx45awSPS0mCzrmeBT5NHyrxYK # 4OtuNQ== # =vzqE # -----END PGP SIGNATURE----- # gpg: Signature made Wed 01 Mar 2023 17:37:41 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20230301' of https://gitlab.com/rth7680/qemu: (62 commits) tcg: Update docs/devel/tcg-ops.rst for temporary changes tcg: Remove tcg_temp_local_new_*, tcg_const_local_* exec/gen-icount: Don't use tcg_temp_local_new_i32 target/xtensa: Don't use tcg_temp_local_new_* target/ppc: Don't use tcg_temp_local_new target/mips: Don't use tcg_temp_local_new target/i386: Don't use tcg_temp_local_new target/hppa: Don't use tcg_temp_local_new target/hexagon/idef-parser: Drop gen_tmp_local target/hexagon: Don't use tcg_temp_local_new_* target/cris: Don't use tcg_temp_local_new target/arm: Don't use tcg_temp_local_new_* target/arm: Drop copies in gen_sve_{ldr,str} tcg: Change default temp lifetime to TEMP_TB tcg: Don't re-use TEMP_TB temporaries accel/tcg/plugin: Tidy plugin_gen_disable_mem_helpers accel/tcg/plugin: Use tcg_temp_ebb_* tcg: Use tcg_constant_ptr in do_dup tcg: Use tcg_temp_ebb_new_* in tcg/ tcg: Add tcg_temp_ebb_new_{i32,i64,ptr} ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
7a819de8 |
| 29-Jan-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hexagon: Don't use tcg_temp_local_new_*
Since tcg_temp_new_* is now identical, use those.
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linar
target/hexagon: Don't use tcg_temp_local_new_*
Since tcg_temp_new_* is now identical, use those.
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
4f9a4cd3 |
| 18-Dec-2022 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-hex-20221216-1' of https://github.com/quic/qemu into staging
1) Performance improvement Add pkt and insn to DisasContext Many functions need information from all 3 structures, so mer
Merge tag 'pull-hex-20221216-1' of https://github.com/quic/qemu into staging
1) Performance improvement Add pkt and insn to DisasContext Many functions need information from all 3 structures, so merge them together.
2) Bug fix Fix predicated assignment to .tmp and .cur
3) Performance improvement Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat These functions will not be handled by idef-parser
4-11) The final 8 patches improve change-of-flow handling.
Currently, we set the PC to a new address before exiting a TB. The ultimate goal is to use direct block chaining. However, several steps are needed along the way.
4) When a packet has more than one change-of-flow (COF) instruction, only the first one taken is considered. The runtime bookkeeping is only needed when there is more than one COF instruction in a packet.
5, 6) Remove PC and next_PC from the runtime state and always use a translation-time constant. Note that next_PC is used by call instructions to set LR and by conditional COF instructions to set the fall-through address.
7, 8, 9) Add helper overrides for COF instructions. In particular, we must distinguish those that use a PC-relative address for the destination. These are candidates for direct block chaining later.
10) Use direct block chaining for packets that have a single PC-relative COF instruction. Instead of generating the code while processing the instruction, we record the effect in DisasContext and generate the code during gen_end_tb.
11) Use direct block chaining for tight loops. We look for TBs that end with an endloop0 that will branch back to the TB start address.
12-21) Instruction definition parser (idef-parser) from rev.ng Parses the instruction semantics and generates TCG
# gpg: Signature made Fri 16 Dec 2022 20:41:53 GMT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422
* tag 'pull-hex-20221216-1' of https://github.com/quic/qemu: (21 commits) target/hexagon: import additional tests target/hexagon: call idef-parser functions target/hexagon: import parser for idef-parser target/hexagon: import lexer for idef-parser target/hexagon: prepare input for the idef-parser target/hexagon: introduce new helper functions target/hexagon: make helper functions non-static target/hexagon: make slot number an unsigned target/hexagon: import README for idef-parser target/hexagon: update MAINTAINERS for idef-parser Hexagon (target/hexagon) Use direct block chaining for tight loops Hexagon (target/hexagon) Use direct block chaining for direct jump/branch Hexagon (target/hexagon) Add overrides for various forms of jump Hexagon (target/hexagon) Add overrides for compound compare and jump Hexagon (target/hexagon) Add overrides for direct call instructions Hexagon (target/hexagon) Remove next_PC from runtime state Hexagon (target/hexagon) Remove PC from the runtime state Hexagon (target/hexagon) Only use branch_taken when packet has multi cof Hexagon (target/hexagon) Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat Hexagon (target/hexagon) Fix predicated assignment to .tmp and .cur ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v7.2.0 |
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#
95e11505 |
| 23-Sep-2022 |
Alessandro Di Federico <ale@rev.ng> |
target/hexagon: import README for idef-parser
Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Rev
target/hexagon: import README for idef-parser
Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220923173831.227551-3-anjo@rev.ng>
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