Home
last modified time | relevance | path

Searched refs:opcodes (Results 1 – 25 of 55) sorted by relevance

123

/openbmc/openbmc/poky/meta/recipes-devtools/binutils/binutils/
H A D0007-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch13 opcodes/ppc-opc.c | 4 +---
16 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
18 --- a/opcodes/ppc-opc.c
19 +++ b/opcodes/ppc-opc.c
/openbmc/qemu/target/xtensa/
H A Dxtensa-isa.c243 isa->opname_lookup_table[n].key = isa->opcodes[n].name; in xtensa_isa_init()
692 encode_fn = intisa->opcodes[opc].encode_fns[slot_id]; in xtensa_opcode_encode()
697 intisa->opcodes[opc].name, slot, intisa->formats[fmt].name); in xtensa_opcode_encode()
710 return intisa->opcodes[opc].name; in xtensa_opcode_name()
719 if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_BRANCH) != 0) { in xtensa_opcode_is_branch()
731 if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_JUMP) != 0) { in xtensa_opcode_is_jump()
743 if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_LOOP) != 0) { in xtensa_opcode_is_loop()
755 if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_CALL) != 0) { in xtensa_opcode_is_call()
768 iclass_id = intisa->opcodes[opc].iclass_id; in xtensa_opcode_num_operands()
779 iclass_id = intisa->opcodes[opc].iclass_id; in xtensa_opcode_num_stateOperands()
[all …]
H A Dhelper.c95 unsigned opcodes; in init_libisa() local
102 opcodes = xtensa_isa_num_opcodes(config->isa); in init_libisa()
105 config->opcode_ops = g_new(XtensaOpcodeOps *, opcodes); in init_libisa()
111 for (i = 0; i < opcodes; ++i) { in init_libisa()
H A Dxtensa-isa-internal.h190 xtensa_opcode_internal *opcodes; member
/openbmc/qemu/tcg/mips/
H A Dtcg-target-opc.h.inc1 /* No target specific opcodes. */
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target-opc.h.inc1 /* No target specific opcodes. */
/openbmc/qemu/tcg/tci/
H A Dtcg-target-opc.h.inc2 /* These opcodes for use between the tci generator and interpreter. */
H A DREADME28 The bytecode consists of opcodes (with only a few exceptions, with
56 registers or additional opcodes (it is easy to modify the virtual machine).
114 * Some TCG opcodes are either missing in the code generator and/or
115 in the interpreter. These opcodes raise a runtime exception, so it is
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-security/trusted-services/corstone1000/
H A D0001-Add-stub-capsule-update-service-components.patch24 protocols/service/capsule_update/opcodes.h | 17 +++
32 create mode 100644 protocols/service/capsule_update/opcodes.h
328 +#include <protocols/service/capsule_update/opcodes.h>
332 diff --git a/protocols/service/capsule_update/opcodes.h b/protocols/service/capsule_update/opcodes.h
336 +++ b/protocols/service/capsule_update/opcodes.h
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target-opc.h.inc9 * Target-specific opcodes for host vector expansion. These will be
/openbmc/qemu/tcg/riscv/
H A Dtcg-target-opc.h.inc9 * Target-specific opcodes for host vector expansion. These will be
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target-opc.h.inc9 * Target-specific opcodes for host vector expansion. These will be
/openbmc/openbmc/meta-openembedded/meta-oe/dynamic-layers/selinux/recipes-devtool/android-tools/android-tools/debian/external/libunwind/
H A D20150704-CVE-2015-3239_dwarf_i.h.patch4 libunwind 1.1 allows local users to have unspecified impact via invalid dwarf opcodes.
/openbmc/qemu/tcg/arm/
H A Dtcg-target-opc.h.inc9 * Target-specific opcodes for host vector expansion. These will be
/openbmc/qemu/tcg/s390x/
H A Dtcg-target-opc.h.inc9 * Target-specific opcodes for host vector expansion. These will be
/openbmc/u-boot/lib/
H A Dslre.c39 } opcodes[] = { variable
109 (void) fprintf(fp, "%s", opcodes[p[i]].name); in print_character_set()
126 (void) fprintf(fp, "%3d %s ", pc, opcodes[op].name); in slre_dump()
128 for (i = 0; opcodes[op].flags[i] != '\0'; i++) in slre_dump()
129 switch (opcodes[op].flags[i]) { in slre_dump()
/openbmc/openbmc/poky/meta/recipes-devtools/gdb/
H A Dgdb-cross-canadian.inc35 # we don't want gdb to provide bfd/iberty/opcodes, which instead will override the
H A Dgdb-common.inc54 # we don't want gdb to provide bfd/iberty/opcodes, which instead will override the
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/enscript/enscript/
H A D0001-enscript-does-not-build-with-C23-standard.patch32 expressions. Some opcodes are followed by argument bytes. A
/openbmc/qemu/tcg/ppc/
H A Dtcg-target-opc.h.inc22 * Target-specific opcodes for host vector expansion. These will be
/openbmc/qemu/tcg/i386/
H A Dtcg-target-opc.h.inc22 * Target-specific opcodes for host vector expansion. These will be
/openbmc/u-boot/include/bedbug/
H A Dppc.h389 extern struct opcode opcodes[];
H A Dtables.h66 struct opcode opcodes[] = { variable
481 const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]);
/openbmc/u-boot/common/
H A Dbedbug.c429 ptr = &opcodes[idx]; in find_opcode()
468 if (!strcmp (name, opcodes[idx].name)) in find_opcode_by_name()
469 return &opcodes[idx]; in find_opcode_by_name()
/openbmc/qemu/docs/devel/
H A Dtcg-ops.rst437 for consistency with the other bswap opcodes. For future
484 not see either 0 or N as inputs for these opcodes.
587 All this opcodes assume that the pointed host memory doesn't correspond
631 opcodes must not be mixed.
673 can obtain the same results by emitting a pair of opcodes, mul + muluh/mulsh.
702 The following opcodes are internal to TCG. Thus they are to be implemented by
923 **Note 2**: When using TCG, the opcodes must never be generated directly
924 as some of them may not be available as "real" opcodes. Always use the

123