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Searched refs:nvbios_rd32 (Results 1 – 25 of 34) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dvmap.c36 vmap = nvbios_rd32(bios, bit_P.offset + 0x20); in nvbios_vmap_table()
101 info->min = nvbios_rd32(bios, vmap + 0x00); in nvbios_vmap_entry_parse()
102 info->max = nvbios_rd32(bios, vmap + 0x04); in nvbios_vmap_entry_parse()
103 info->arg[0] = nvbios_rd32(bios, vmap + 0x08); in nvbios_vmap_entry_parse()
104 info->arg[1] = nvbios_rd32(bios, vmap + 0x0c); in nvbios_vmap_entry_parse()
105 info->arg[2] = nvbios_rd32(bios, vmap + 0x10); in nvbios_vmap_entry_parse()
110 info->min = nvbios_rd32(bios, vmap + 0x02); in nvbios_vmap_entry_parse()
111 info->max = nvbios_rd32(bios, vmap + 0x06); in nvbios_vmap_entry_parse()
112 info->arg[0] = nvbios_rd32(bios, vmap + 0x0a); in nvbios_vmap_entry_parse()
113 info->arg[1] = nvbios_rd32(bios, vmap + 0x0e); in nvbios_vmap_entry_parse()
[all …]
H A Dpmu.c37 data = nvbios_rd32(bios, bit_p.offset + 0x00); in nvbios_pmuTe()
69 info->data = nvbios_rd32(bios, data + 0x02); in nvbios_pmuEp()
83 info->init_addr_pmu = nvbios_rd32(bios, data + 0x08); in nvbios_pmuRm()
84 info->args_addr_pmu = nvbios_rd32(bios, data + 0x0c); in nvbios_pmuRm()
86 info->boot_addr_pmu = nvbios_rd32(bios, data + 0x10) + in nvbios_pmuRm()
87 nvbios_rd32(bios, data + 0x18); in nvbios_pmuRm()
89 nvbios_rd32(bios, data + 0x18); in nvbios_pmuRm()
93 info->code_size = nvbios_rd32(bios, data + 0x20); in nvbios_pmuRm()
95 nvbios_rd32(bios, data + 0x24); in nvbios_pmuRm()
96 info->data_addr_pmu = nvbios_rd32(bios, data + 0x28); in nvbios_pmuRm()
[all …]
H A Dvolt.c36 volt = nvbios_rd32(bios, bit_P.offset + 0x0c); in nvbios_volt_table()
39 volt = nvbios_rd32(bios, bit_P.offset + 0x10); in nvbios_volt_table()
92 info->base = nvbios_rd32(bios, volt + 0x04); in nvbios_volt_parse()
98 info->max = nvbios_rd32(bios, volt + 0x0e); in nvbios_volt_parse()
103 info->min = nvbios_rd32(bios, volt + 0x0a); in nvbios_volt_parse()
104 info->max = nvbios_rd32(bios, volt + 0x0e); in nvbios_volt_parse()
108 if (nvbios_rd32(bios, volt + 0x4) & 1) { in nvbios_volt_parse()
110 info->pwm_freq = nvbios_rd32(bios, volt + 0x5) / 1000; in nvbios_volt_parse()
111 info->pwm_range = nvbios_rd32(bios, volt + 0x16); in nvbios_volt_parse()
155 info->voltage = nvbios_rd32(bios, volt) & 0x001fffff; in nvbios_volt_entry_parse()
[all …]
H A Dtiming.c37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
140 p->timing[0] = nvbios_rd32(bios, data + 0x00); in nvbios_timingEp()
141 p->timing[1] = nvbios_rd32(bios, data + 0x04); in nvbios_timingEp()
142 p->timing[2] = nvbios_rd32(bios, data + 0x08); in nvbios_timingEp()
143 p->timing[3] = nvbios_rd32(bios, data + 0x0c); in nvbios_timingEp()
144 p->timing[4] = nvbios_rd32(bios, data + 0x10); in nvbios_timingEp()
145 p->timing[5] = nvbios_rd32(bios, data + 0x14); in nvbios_timingEp()
146 p->timing[6] = nvbios_rd32(bios, data + 0x18); in nvbios_timingEp()
147 p->timing[7] = nvbios_rd32(bios, data + 0x1c); in nvbios_timingEp()
[all …]
H A Dpower_budget.c39 power_budget = nvbios_rd32(bios, bit_P.offset + 0x2c); in nvbios_power_budget_table()
115 entry->min_w = nvbios_rd32(bios, entry_offset + 0x2); in nvbios_power_budget_entry()
116 entry->avg_w = nvbios_rd32(bios, entry_offset + 0x6); in nvbios_power_budget_entry()
117 entry->max_w = nvbios_rd32(bios, entry_offset + 0xa); in nvbios_power_budget_entry()
120 entry->max_w = nvbios_rd32(bios, entry_offset + 0x2); in nvbios_power_budget_entry()
H A Dpll.c90 data = nvbios_rd32(bios, bit_C.offset + 0); in pll_limits_table()
153 if (nvbios_rd32(bios, data + 3) == reg) { in pll_map_reg()
168 if (nvbios_rd32(bios, data) == map->reg) in pll_map_reg()
197 *reg = nvbios_rd32(bios, data + 3); in pll_map_type()
213 if (nvbios_rd32(bios, data) == map->reg) in pll_map_type()
257 info->vco1.min_freq = nvbios_rd32(bios, data + 0); in nvbios_pll_parse()
258 info->vco1.max_freq = nvbios_rd32(bios, data + 4); in nvbios_pll_parse()
259 info->vco2.min_freq = nvbios_rd32(bios, data + 8); in nvbios_pll_parse()
260 info->vco2.max_freq = nvbios_rd32(bios, data + 12); in nvbios_pll_parse()
327 info->refclk = nvbios_rd32(bios, data + 31); in nvbios_pll_parse()
[all …]
H A Dinit.c629 u32 reg = nvbios_rd32(bios, init->offset + 7); in init_io_restrict_prog()
639 u32 data = nvbios_rd32(bios, init->offset); in init_io_restrict_prog()
693 u32 reg = nvbios_rd32(bios, init->offset + 8); in init_io_restrict_pll()
743 u32 reg = nvbios_rd32(bios, init->offset + 1); in init_copy()
968 u32 freq = nvbios_rd32(bios, init->offset); in init_io_restrict_pll2()
1291 u32 data = nvbios_rd32(bios, init->offset); in init_zm_reg_sequence()
1330 u32 data = nvbios_rd32(bios, addr); in init_zm_reg_indirect()
1545 data = nvbios_rd32(bios, mdata); in init_configure_mem()
1924 u32 freq = nvbios_rd32(bios, init->offset); in init_ram_restrict_pll()
1997 u32 data = nvbios_rd32(bios, init->offset); in init_ram_restrict_zm_reg_group()
[all …]
H A Ddcb.c48 if (nvbios_rd32(bios, dcb + 6) == 0x4edcbdcb) { in dcb_table()
56 if (nvbios_rd32(bios, dcb + 4) == 0x4edcbdcb) { in dcb_table()
128 u32 conn = nvbios_rd32(bios, dcb + 0x00); in dcb_outp_parse()
142 u32 conf = nvbios_rd32(bios, dcb + 0x04); in dcb_outp_parse()
219 if (nvbios_rd32(bios, outp) == 0x00000000) in dcb_outp_foreach()
221 if (nvbios_rd32(bios, outp) == 0xffffffff) in dcb_outp_foreach()
H A DP0260.c37 data = nvbios_rd32(bios, bit_P.offset + 0x60); in nvbios_P0260Te()
75 info->data = nvbios_rd32(bios, data); in nvbios_P0260Ep()
101 info->data = nvbios_rd32(bios, data); in nvbios_P0260Xp()
H A Dnpde.c35 switch (nvbios_rd32(bios, data + 0x00)) { in nvbios_npdeTe()
41 data, nvbios_rd32(bios, data + 0x00)); in nvbios_npdeTe()
H A Dgpio.c94 u32 info = nvbios_rd32(bios, data); in dcb_gpio_parse()
103 u32 info = nvbios_rd32(bios, data + 0); in dcb_gpio_parse()
104 u8 info1 = nvbios_rd32(bios, data + 4); in dcb_gpio_parse()
H A Dpcir.c33 switch (nvbios_rd32(bios, data + 0x00)) { in nvbios_pcirTe()
43 data, nvbios_rd32(bios, data + 0x00)); in nvbios_pcirTe()
H A Dfan.c36 fan = nvbios_rd32(bios, bit_P.offset + 0x58); in nvbios_fan_table()
90 fan->pwm_freq = nvbios_rd32(bios, data + 0x0b) & 0xffffff; in nvbios_fan_parse()
H A Dperf.c38 perf = nvbios_rd32(bios, bit_P.offset + 0); in nvbios_perf_table()
105 info->core = nvbios_rd32(bios, perf + 0x01) * 10; in nvbios_perfEp()
106 info->memory = nvbios_rd32(bios, perf + 0x05) * 20; in nvbios_perfEp()
H A DM0209.c37 data = nvbios_rd32(bios, bit_M.offset + 0x09); in nvbios_M0209Te()
125 info->data[i] = nvbios_rd32(bios, data + off); in nvbios_M0209Sp()
H A Dtherm.c36 therm = nvbios_rd32(bios, bit_P.offset + 12); in therm_table()
38 therm = nvbios_rd32(bios, bit_P.offset + 16); in therm_table()
H A Dvpstate.c35 return nvbios_rd32(b, bit_P.offset + 0x38); in nvbios_vpstate_offset()
H A Diccsense.c40 iccsense = nvbios_rd32(bios, bit_P.offset + 0x28); in nvbios_iccsense_table()
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramgp100.c56 data = nvbios_rd32(bios, data + 0x10); /* guess u32... */ in gp100_ram_init()
62 nvbios_init(subdev, nvbios_rd32(bios, data)); in gp100_ram_init()
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dgm200.c43 nvkm_wr32(device, 0x10a184, nvbios_rd32(bios, img + i)); in pmu_code()
61 nvkm_wr32(device, 0x10a1c4, nvbios_rd32(bios, img + i)); in pmu_data()
H A Dnv05.c83 u32 scramble = nvbios_rd32(bios, data); in nv05_devinit_meminit()
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dbios.h31 u32 nvbios_rd32(struct nvkm_bios *, u32 addr);
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgm107.c317 u32 data = nvbios_rd32(bios, bit_P.offset + 0x28); in gm107_gr_init_bios_2()
322 data = nvbios_rd32(bios, data + 0x04); in gm107_gr_init_bios_2()
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
H A Dgf119.c36 u32 data = nvbios_rd32(bios, entry); in gf119_gpio_reset()
H A Dga102.c34 u32 data = nvbios_rd32(bios, entry); in ga102_gpio_reset()

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